參數(shù)資料
型號(hào): M95160-R
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
中文描述: 16千位和8千位串行SPI高速時(shí)鐘總線的EEPROM
文件頁(yè)數(shù): 44/45頁(yè)
文件大?。?/td> 270K
代理商: M95160-R
Revision history
M95160, M95080
44/45
24-May-2007
6
Document reformatted. Small text changes.
TSSOP8 3 x 3 mm (DS) package removed, 1.65 V to 5.5 V operating
voltage range removed (M95080-S and M95160-S removed).
Figure 4: Bus master and memory devices on the SPI bus
updated, note 2
removed and explanatory paragraph added (see
Section 3: Connecting to
the SPI bus
).
Section 2.7: VCC supply voltage
and
Section 2.8: VSS ground
added.
Power-up, Device Internal Reset and Power-down replaced by
Section 4.1: Supply voltage (VCC)
.
Command termination specified in
Section 6.4: Write Status Register
(WRSR)
.
Blank process no longer available for M95160, M95080, M95160-W and
M95080-W in the device grade 3 range.
L, GB and SB processes no longer available for M95160 and M95080, in
the device grade 6 range.
L process no longer available for M95160-W and M95080-W in the device
grade 6 range.
I
CC1
value and test conditions modified in
Table 18: DC characteristics
(M95160-R and M95080-R)
.
End timing line of t
SHQZ
modified in
Figure 17: Output timing
.
SO8N and UFDFPN8 package specifications updated. All packages are
ECOPACK compliant.
Blank option removed below Plating technology and Note 2 modified in
Table 27: Ordering information scheme
.
Table 28: Available M95160 products (package, voltage range,
temperature grade)
and
Table 29: Available M95080 products (package,
voltage range, temperature grade)
added.
Table 30.
Document revision history
Date
Revision
Changes
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