參數(shù)資料
型號: MACH1
廠商: Lattice Semiconductor Corporation
英文描述: High-Performance EE CMOS Programmable Logic
中文描述: 高性能電子工程CMOS可編程邏輯
文件頁數(shù): 13/48頁
文件大?。?/td> 1136K
代理商: MACH1
20
MACH 1 & 2 Families
BLOCK DIAGRAM (MACH131, MACH131SP)
I/O Cells
Macrocells
I/O48 – I/O63
52 x 70
AND Logic Array
and
Logic Allocator
OE
I/O Cells
Macrocells
I/O16 – I/O31
52 x 70
AND Logic Array
and
Logic Allocator
OE
16
26
Switch Matrix
I/O Cells
Macrocells
I/O0 – I/O15
I2, I5
52 x 70
AND Logic Array
and
Logic Allocator
CLK0/I0, CLK1/I1
CLK2/I3, CLK3/I4
OE
16
26
2
4
16
26
I/O Cells
Macrocells
I/O32 – I/O47
52 x 70
AND Logic Array
and
Logic Allocator
OE
16
26
4
Block A
Block B
Block D
Block C
14051K-009
16
相關(guān)PDF資料
PDF描述
MACH210A-10JC High-Density EE CMOS Programmable Logic
MACH210A-10VC High-Density EE CMOS Programmable Logic
MACH210A-12JC High-Density EE CMOS Programmable Logic
MACH210A-12VC High-Density EE CMOS Programmable Logic
MACH210A-7 High-Density EE CMOS Programmable Logic
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