參數(shù)資料
型號(hào): MACH1
廠商: Lattice Semiconductor Corporation
英文描述: High-Performance EE CMOS Programmable Logic
中文描述: 高性能電子工程CMOS可編程邏輯
文件頁(yè)數(shù): 29/48頁(yè)
文件大?。?/td> 1136K
代理商: MACH1
MACH 1 & 2 Families
35
44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input
GND
= Ground
I
= Input
I/O
= Input/Output
VCC
= Supply Voltage
TDI
= Test Data In
TCK
= Test Clock
TMS
= Test Mode Select
TDO = Test Data Out
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
1 44 43 42
5
4
3
2
641 40
7
8
9
10
11
12
13
14
15
16
17
23 24 25 26
19 20 21 22
18
27 28
39
38
37
36
35
34
33
32
31
30
29
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
Block B
Block A
14051K-018
相關(guān)PDF資料
PDF描述
MACH210A-10JC High-Density EE CMOS Programmable Logic
MACH210A-10VC High-Density EE CMOS Programmable Logic
MACH210A-12JC High-Density EE CMOS Programmable Logic
MACH210A-12VC High-Density EE CMOS Programmable Logic
MACH210A-7 High-Density EE CMOS Programmable Logic
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