- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180472 > MACH1 (Lattice Semiconductor Corporation) High-Performance EE CMOS Programmable Logic PDF資料下載
參數(shù)資料
| 型號： | MACH1 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | 高性能電子工程CMOS可編程邏輯 |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 1136K |
| 代理商： | MACH1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁
MACH 1 & 2 Families
5
Each PAL block consists of the following elements:
x
Product-term array
x
Logic Allocator
x
Macrocells
x
I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the ip-ops within a single PAL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efcient logic implementation.
Because the number of product terms available for a given function is not xed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Logic Allocator
The logic allocator (Figure 2) is a block within which different product terms are allocated to the
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it ts functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
Table 4. PAL Block Inputs
Device
Number of Inputs to PAL Block
Device
Number of Inputs to PAL Block
MACH111
26
MACH211SP
26
MACH111SP
26
MACH221
26
MACH131
26
MACH221SP
26
MACH131SP
26
MACH231
32
MACH211
26
MACH231SP
32
相關PDF資料 |
PDF描述 |
|---|---|
| MACH210A-10JC | High-Density EE CMOS Programmable Logic |
| MACH210A-10VC | High-Density EE CMOS Programmable Logic |
| MACH210A-12JC | High-Density EE CMOS Programmable Logic |
| MACH210A-12VC | High-Density EE CMOS Programmable Logic |
| MACH210A-7 | High-Density EE CMOS Programmable Logic |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH10015JC | 制造商:AMD 功能描述:NEW |
| MACH102-24TP-F | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 24 PORTS 10/100BASETX, 2 GIG COMBO PORTS |
| MACH102-24TP-FR | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT SWITCH, 24 PORTS 10/100BASETX, 2 COMBO PORTS |
| MACH102-8TP | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 8 PORTS 10/100BASETX, 2 COMBO PORTS |
| MACH102-8TP-F | 制造商:HIRSCHMANN INDUSTRIAL 功能描述:ETHERNET SWITCH, 19 IN. RACK MOUNT, 8 PORTS 10/100BASETX, 2 GIG COMBO PORTS |
發(fā)布緊急采購，3分鐘左右您將得到回復。