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參數(shù)資料
| 型號(hào)： | MAX11040KDBEVKIT# |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR MAX11040 W/FMC CONN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 軟件下載： | MAX11040KEVKIT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.07M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±2.2 V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | MAX11040K |
| 已供物品： | 板 |
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MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
22
Maxim Integrated
DRDYOUT
CS
DATA READ
CHANGE DATA RATE
1
2
15
16
17
DATA AT THE OLD
DATA RATE
DATA AT THE NEW
DATA RATE
Figure 12. Timing Diagram for a Data-Rate Change
The data length of the Data-Rate Control register is 16
bits total for writes and reads (see Table 2). Changes to
the Data-Rate Control register take effect after 16 con-
version periods (Figure 12), i.e., the ADC continues to
operate at the old data rate for another 16 periods. Also,
the last sample at the old data rate (sample 16 in Figure
12) may contain some noise component and should be
discarded. Changes in data rate should be limited to
±5% for correct operation. The data rate register should
not be updated more than once every 32 data rate peri-
ods.
Note: Write to the data rate register in the time window of
10ns after the rising edge of DRDYOUT and 100ns
before the falling edge of DRDYOUT.
The digital filter determines the latency. Latency is
defined as the time between the effective point in time
that a sample is taken and when the resulting digital data
is available for reading (DRDYOUT goes low). The laten-
cy of the converter is specified by the following equation:
Latency = (6 x tDOUT) + (PHI x 1.3μs) + 30μs
where tDOUT is the data output period (inverse of the
programmed sample rate) determined by XINCLOCK
and the selected output data rate, and PHI is the pro-
grammed sampling instant delay for the channel in ques-
tion (0
≤ PHI ≤ 255). The latency is approximately 405μs
at 16ksps.
Because the two filters operate at different output data
rates, a skew builds up between them over the 16 sam-
ples that both are in operation. For example, at 30ksps,
the minimum data rate step size is 0.125%; so over 16
samples, the difference becomes 2%. This causes the
period from sample 16 to sample 17 to be different by
this amount.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11040KDBEVKIT# | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX5135/11040/11612 Eval Kit w/ FMC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX11040KEVKIT | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:MAX11040K Evaluation Kit/Daughterboard |
| MAX11040KEVKIT# | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX5135/11040/11612 Eval Kit w/ FMC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX11040KGUU | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
| MAX11040KGUU/GG8 | 制造商:Maxim Integrated Products 功能描述:24-BIT, 4-CHANNEL, SIMULTANEOUS-SAMPLING, CASCADABLE, SIGMA- - Rail/Tube |
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