參數(shù)資料
型號: MAX11040KDBEVKIT#
廠商: Maxim Integrated Products
文件頁數(shù): 4/35頁
文件大?。?/td> 0K
描述: KIT EVAL FOR MAX11040 W/FMC CONN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
軟件下載: MAX11040KEVKIT
標準包裝: 1
ADC 的數(shù)量: 4
位數(shù): 24
采樣率(每秒): 3.07M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
輸入范圍: ±2.2 V
工作溫度: -40°C ~ 105°C
已用 IC / 零件: MAX11040K
已供物品:
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
12
Maxim Integrated
Detailed Description
The MAX11040K/MAX11060 are 24-/16-bit, simultane-
ous-sampling, 4-channel, sigma-delta ADCs including
support for synchronized sampling and daisy chaining
of the serial interface across multiple (up to eight)
devices. The serial interface of the set of synchronized
devices behaves as one device. Each channel includes
a differential analog input, a sigma-delta modulator, a
digital decimation filter, an independent programmable
sampling delay, and a buffered reference signal from
the internal or an external reference. The device con-
tains an internal crystal oscillator. The output data rate,
the effective sample rate of the ADC, is software pro-
grammable.
The devices operate from a single 3.0V to 3.6V analog
supply and a 2.7V to VAVDD digital supply. The 4-wire
serial interface is SPI/QSPI/MICROWIRE and DSP com-
patible.
ADC Modulator
Each channel of the devices performs analog-to-
digital conversion on its input using a dedicated
switched-capacitor sigma-delta modulator. The modula-
tor converts the input signal into low-resolution digital data
for which the average value represents the digitized sig-
nal information at 3.072Msps for a 24.576MHz XIN clock.
This data stream is then presented to the digital filter for
processing to remove the high-frequency noise that cre-
ates a high-resolution 24-/16-bit output data stream.
The input sampling network of the analog input consists
of a pair of 4pF capacitors (CSAMPLE), the bottom
plates of which are connected to AIN_+ and AIN_- dur-
ing the track phase and then shorted together during
the hold phase (see Figure 1). The internal switches
have a total series resistance of 400
Ω. Given a
24.576MHz XIN clock, the switching frequency is
3.072MHz. The sampling phase lasts for 120ns.
MAX11040K
MAX11060
CSAMPLE+
HOLD
TO ADC
RON
CSAMPLE-
TRACK
AIN_+
AIN_-
AVDD/2
Figure 1. Simplified Track/Hold Stage
MAX11040K
MAX11060
AIN0+
AIN0-
1
F
AIN0-
AIN0+
24.576MHz
REF0
AIN1+
AIN1-
1
F
AIN1-
AIN1+
REF1
AIN2+
AIN2-
1
F
AIN2-
AIN2+
REF2
AIN3+
AIN3-
1
F
AIN3-
AIN3+
REF3
1
F
REFIO
0.01
F
1
F
3.3V
AVDD
0.01
F
1
F
3.3V
DVDD
20pF
XIN
XOUT
CLKOUT
CASCOUT
CASCIN
DOUT
DRDYOUT
DIN
SCLK
CS
SYNC
DRDYIN
FAULT
OVRFLW
MICROCONTROLLER
OR DSP
AGND
DGND
Typical Operating Circuit
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