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    參數(shù)資料
    型號: MAX11040KDBEVKIT#
    廠商: Maxim Integrated Products
    文件頁數(shù): 7/35頁
    文件大小: 0K
    描述: KIT EVAL FOR MAX11040 W/FMC CONN
    產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
    Obsolescence Mitigation Program
    軟件下載: MAX11040KEVKIT
    標(biāo)準(zhǔn)包裝: 1
    ADC 的數(shù)量: 4
    位數(shù): 24
    采樣率(每秒): 3.07M
    數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
    輸入范圍: ±2.2 V
    工作溫度: -40°C ~ 105°C
    已用 IC / 零件: MAX11040K
    已供物品:
    MAX11040K/MAX11060
    24-/16-Bit, 4-Channel, Simultaneous-Sampling,
    Cascadable, Sigma-Delta ADCs
    15
    Maxim Integrated
    When the analog input voltage changes between the
    ADC full scale and the fault threshold faster than the
    latency of the converter, OVRFLW goes low with the
    FAULT output. OVRFLW remains invalid until a valid
    clock frequency is available at XIN.
    Overvoltage-Fault Detection and Recovery (
    FAULT)
    With overvoltage-fault protection enabled (FAULTDIS =
    0), FAULT immediately transitions from a high to low
    when any of the analog inputs go outside the voltage
    range bounded by the fault-detection thresholds VPFT
    and VNFT.
    Once the analog inputs return back within the fault
    thresholds, the FAULT interrupt output goes high after a
    delay called the fault-recovery time. The fault-recovery
    time is:
    20 x tDOUT < fault-recovery time < 25 x tDOUT
    where tDOUT is the data output period determined by
    fXINCLOCK and the selected output data rate.
    In the event the analog input voltage changes between
    the ADC full scale and the fault threshold faster than
    the latency of the converter, the ADC conversion result
    prematurely jumps to the full-scale value when a fault is
    detected (see Detection Discontinuity in Figure 4).
    During a fault condition and the subsequent fault-
    recovery time, the ADC conversion result remains at full
    scale. This creates a discontinuity in the digital conver-
    sion result only if the fault recovery time is greater than
    the latency plus the time that the input changes
    between the fault threshold and the ADC full scale (see
    Recovery Discontinuity in Figure 4). Neither of these
    steps occur if the fault-protection circuitry is disabled
    (FAULTDIS = 1), or if the input is slow relative to the
    above descriptions (see Figure 5).
    For data rates faster than 32ksps (FSAMPC = 111), the
    converter output may contain invalid data for up to
    188μs after FAULT returns high. To prevent this behav-
    ior, disable the overvoltage-fault protection by setting
    the FAULTDIS bit in the configuration register to 1 when
    using FSAMPC = 111, and limit the analog input swing
    to ±3.5V.
    |AIN+ - AIN-|
    LATENCY
    DETECTION
    DISCONTINUITY
    RECOVERY
    DISCONTINUITY
    FULL SCALE
    (|0.88VREF|)
    FAULT-DETECTION
    THRESHOLD
    (VPFT OR |VNFT|)
    RECOVERY TIME
    LATENCY
    FAULT
    OVRFLW
    DIGITAL OUTPUT
    DATA AT DOUT
    Figure 4. High-Frequency Analog Input Overvoltage Detection and Recovery
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    參數(shù)描述
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