參數(shù)資料
型號： MB81V17805A-70L
廠商： Fujitsu Limited
英文描述： CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 200萬× 8位超頁模式動態(tài)RAM的CMOS（200萬× 8位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 11/30頁
文件大?。?/td> 604K
代理商： MB81V17805A-70L
11
MB81V17805A-60/-60L/-70/-70L
Notes:
*1. Referenced to V
SS
.
*2. I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open.
I
CC
depends on the number of address change as RAS = V
IL
CAS = V
IH
and V
IL
> –0.3 V.
I
CC1
, I
CC3
I
CC4
and I
CC5
are specified at one time of address change during RAS = V
IL
and CAS = V
IH
I
CC2
is specified during RAS = V
IH
and V
IL
> –0.3 V.
I
CC6
is measured on condition that all address signals are fixed steady state.
*3. An initial pause (RAS = CAS = V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-
only cycles before proper device operation is achieved. In case of using internal refresh counter, a
minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
*4. AC characteristics assume t
T
= 2 ns.
*5. Input voltage levels are 0 V and 3 V, and input reference levels are V
IH
(min) and V
IL
(max) for measuring
timing of input signals. Also, the transition time(t
T
) is measured between V
IH
(min)and V
IL
(max).
The output reference levels are V
OH
= 2.0 V and V
OL
= 0.8 V.
*6. Assumes that t
RCD
≤
t
RCD
(max), t
RAD
≤
t
RAD
(max). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown.
Refer to Fig.2 and 3.
*7. If t
RCD
≥
t
RCD
(max), t
RAD
≥
t
RAD
(max), and t
ASC
≥
t
AA
- t
CAC
- t
T
, access time is t
CAC
.
*8. If t
RAD
≥
t
RAD
(max) and t
ASC
≤
t
AA
- t
CAC
- t
T
, access time is t
AA
.
*9. Measured with a load equivalent to one TTL load and 100 pF.
*10. t
OFR,
t
WEZ,
t
OFF
and t
OEZ
are specified that output buffer change to high impedance state.
*11. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
*12. t
RCD
(min) = t
RAH
(min) + 2t
T
+ t
ASC
(min).
*13. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
*14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
*15. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min) the data output pin will remain High-Z
state through entire cycle.
*16. Assumes that t
WCS
< t
WCS
(min).
*17. Either t
DZC
or t
DZO
must be satisfied.
*18. t
CPA
is access time from the selection of a new column address (that is caused by changing both CAS
from “L” to “H”).
Therefore, if t
CP
is long, t
CPA
is longer than t
CPA
(max).
*19. Assumes that CAS-before-RAS refresh.
*20. t
WCS
, t
CWD
, t
RWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet
as an electrical characteristic only. If t
WCS
> t
WCS
(min), the cycle is an early write cycle and D
OUT
pin
will maintain high-impedance state through out the entire cycle. If t
CWD
> t
CWD
(min), t
RWD
> t
RWD
(min),
and t
AWD
> t
AWD
(min), the cycle is a read-modify-write cycle and data from the selected cell will appear
at the D
OUT
pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and
invalid data will appear the D
OUT
pin, and write operation can be executed by satisfying t
RWL
, t
CWL
, and
t
RAL
specifications.
*21. The last CAS rising edge.
*22. The first CAS falling edge.
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