參數(shù)資料
型號(hào)： MB81V17805A-70L
廠商： Fujitsu Limited
英文描述： CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 200萬× 8位超頁模式動(dòng)態(tài)RAM的CMOS（200萬× 8位超級(jí)頁面存取模式動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 27/30頁
文件大?。?/td> 604K
代理商： MB81V17805A-70L
27
MB81V17805A-60/-60L/-70/-70L
CAS
Fig. 20 – SELF REFRESH CYCLE (A
0
to A
11
= WE = OE = “H” or “L”)
(At recommended operating conditions unless otherwise noted.)
Note:
Assumes Self Refresh cycle only.
Parameter
Unit
Min.
100
124
–50
Max.
—
—
—
No.
Min.
100
104
–50
Max.
—
74
75
76
Symbol
—
—
μ
s
ns
ns
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
MB81V17805A-60/60L MB81V17805A-70/70L
t
RASS
t
RPS
t
CHS
DESCRIPTION
The Self Refresh cycle provides a refresh operation without external clock and external Address. Self Refresh control circuit on chip is
operated in the Self Refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing
generator.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than 100
μ
s),
the device can enter the Self Refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal
refresh address counter during “RAS=L” and “CAS=L”.
Exit from self refresh cycle is performed by toggling RAS and CAS to “H” with specified t
CHS
min. In this time, RAS must be kept “H” with
specified t
RPS
min.
Using Self Refresh mode, data can be retained without external CAS signal during system is in standby.
Restriction for Self Refresh operation ;
For Self Refresh operation, the notice below must be considered.
1) In the case that distributed CBR refresh are operated between read/write cycles
Self Refresh cycles can be executed without special rule if 2,048 cycles of distributed CBR refresh are executed within t
REF
max.
2) In the case that burst CBR refresh or distributed/burst RAS-only refresh are operated between read/write cycles
2,048 times of burst CBR refresh or 2,048 times of burst RAS-only refresh must be executed before and after Self Refresh
cycles.
V
IH
V
IL
RAS
V
IH
V
IL
RAS
V
IH
V
IL
V
OH
V
OL
DQ
(Output)
HIGH-Z
t
RASS
t
RPS
t
RPC
t
CHS
t
CSR
t
CPN
t
OFF
t
OH
* Read/Write operation can be performed non refresh time within t
NS
or t
SN
2,048 burst refresh cycle
2,048 burst refresh cycle
Read/Write operation
Self Refresh operation
t
RASS
Read/Write operation
t
NS
< 2 ms
t
SN
< 2 ms
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
*
*
相關(guān)PDF資料
PDF描述
MB81V17805B-50 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB81V17805B-60 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB81V18160A-70 CMOS 1M ×16 BIT Fast Page Mode Dynamic RAM(CMOS 1M ×16 位快速頁面存取模式動(dòng)態(tài)RAM)
MB81V18160A-70L CMOS 1M ×16 BIT Fast Page Mode Dynamic RAM(CMOS 1M ×16 位快速頁面存取模式動(dòng)態(tài)RAM)
MB81V18165A-70 CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
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