參數(shù)資料
型號(hào)： MB81V18165A-70L
廠商： Fujitsu Limited
英文描述： CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 100萬× 16位的超頁模式動(dòng)態(tài)RAM的CMOS（100萬× 16位超級(jí)頁面存取模式動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 26/30頁
文件大?。?/td> 681K
代理商： MB81V18165A-70L
26
MB81V18165A-60/60L/-70/70L
—
—
—
—
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held
Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
9
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
7
are defined by latching levels on A
0
-A
7
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 1,024 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS refresh
counter test (read-modify-write cycles). Repeat this procedure 1,024 times with addresses generated by the internal refresh
address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.)
t
DZC
t
RCS
LCAS
or
UCAS
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
9
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
DQ
(Output)
t
CSR
t
RP
t
CP
t
FCAH
t
ASC
t
CWL
t
WP
t
CHR
t
FRSH
t
FCAS
t
RWL
t
FCWD
t
DH
t
DS
t
OED
t
OEA
t
DZO
t
OEH
VALID DATA IN
COLUMN ADDRESSES
t
FCAC
HIGH-Z
HIGH-Z
HIGH-Z
t
OEZ
t
ON
Valid Data
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
MB81V18165A-70/70L
Min
.
—
MB81V18165A-60/60L
Min.
—
Unit
Parameter
Max.
55
ns
ns
ns
ns
ns
No
.
Max.
50
—
—
—
—
69
70
71
72
73
Symbol
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
35
77
99
99
35
70
90
90
Column Address Hold Time
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
相關(guān)PDF資料
PDF描述
MB81V18165B-50 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB81V18165B-60 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
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MB81V4100C-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動(dòng)態(tài)RAM)
MB81V4260S-60 CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁面存取模式動(dòng)態(tài)RAM)
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