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參數(shù)資料
| 型號： | MB81V4100C-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 1位快速頁面模式的DRAM（的CMOS 4米× 1位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 397K |
| 代理商： | MB81V4100C-70 |
16
MB81V4100C-60/MB81V4100C-70
HIGH-Z
ROW ADDRESS
“H” or “L”
DESCRIPTION
The CAS-before-RAS refresh is executed by bringing CAS “L” before RAS. By this timing combination, the MB81V4100C executes
CAS-before-RAS refresh. The row address input is not necessary because it is generated internally.
WE must be held “H” for the specified set up time (t
WSR
) before RAS goes “L” in order not to enter “test mode”.
Fig. 11 – RAS-ONLY REFRESH (WE, D
IN
, A
10
= “H” or “L”)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
D
OUT
A
0
to A
9
t
RAH
t
RC
DESCRIPTION
The refresh of DRAM is executed by normal read, write or read-modify-write cycle, i.e., the cells on the one row line are also
refreshed by executing one of three cycles. 1024 row address must be refreshed every 16.4ms period. During the refresh cycle,
the cell data connected to the selected row are sent to sense amplifier and re-written to the cell. The MB81V4100C has three types
of refresh modes, RAS-only refresh, CAS-before-RAS refresh, and Hidden refresh.
The RAS-only refresh is executed by keeping RAS “L” and CAS “H” throughout the cycle. The row address to be refreshed is
latched on the falling edge of RAS. During RAS-only refresh, the D
OUT
pin is kept in a high impedance state.
Fig. 12 – CAS-BEFORE-RAS REFRESH (A
0
to A
10
, D
IN
= “H” or “L”)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
D
OUT
WE
t
ASR
t
CRP
t
RAS
t
RPC
t
RP
HIGH-Z
“H” or “L”
t
RP
t
RAS
t
RPC
t
CHR
t
CSR
t
CPN
t
WSR
t
WHR
t
OFF
t
OH
t
OFF
t
OH
t
RC
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