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| 型號： | MB81V4100C-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 1位快速頁面模式的DRAM（的CMOS 4米× 1位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 18/23頁 |
| 文件大小： | 397K |
| 代理商： | MB81V4100C-70 |
18
MB81V4100C-60/MB81V4100C-70
Fig. 14 – TEST MODE SET CYCLE (A
0
to A
10
, D
IN
= “H” or “L”)
DESCRIPTION
Test Mode;
The purpose of this test mode is to reduce device test time to one eighth of that required to test the device conventionally.
The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of
RA10, CA0 and CA10. In the write mode, data at D
IN
is written into eight cells simultaneously. In the read mode, eight cells at the
selected addresses are read back and checked in the following manner.
When the eight bits are all “L” or all “H”, a “H” level is output..
When the eight bits show a combination of “L” and “H”, a “L” level is output..
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 5ns from the specified value in the data sheet..
t
RC
, t
RWC
, t
RAC
, t
AA
, t
RAS
, t
CSH
, t
RAL
, t
RWD
, t
AWD
, t
PC
, t
PRWC
, t
CPA
, t
RHCP
, t
CPWD
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
WE
DQ
(Output)
HIGH-Z
“H” or “L”
t
RP
t
RC
t
RAS
t
RPC
t
CHR
t
CSR
t
CPN
t
WSR
t
WHR
t
OFF
t
OH
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