參數(shù)資料
型號(hào)： MB81V4265S-60L
廠商： Fujitsu Limited
英文描述： CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 256K × 16位的超頁(yè)模式動(dòng)態(tài)RAM的CMOS（256K × 16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 26/30頁(yè)
文件大小： 653K
代理商： MB81V4265S-60L
26
MB81V4265S-60/-70/-60L/-70L
LCAS
or
UCAS
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
Parameter
Unit
Min.
—
30
80
55
55
85
Max.
55
—
—
—
—
—
μ
s
ns
ns
μ
s
ns
ns
No.
Min.
—
30
80
55
55
85
Max.
55
—
—
—
—
—
(At recommended operating conditions unless otherwise noted.)
MB81V4265S-60/60L
Symbol
MB81V4265S-70/70L
Access Time from CAS
Column Address Hold Time
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
CAS Hold Time
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
8
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
90
91
92
93
94
95
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
t
FCSH
“H” or “L”
Valid Data
COLUMN ADDRESS
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the
functionality of CAS-before-RAS refresh circuitry. After a CAS-before-RAS refresh cycle, if LCAS or UCAS makes a transition from
High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are
defined as follows:
Row Address: Bits A
0
through A
8
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
8
are defined by latching levels on A
0
to A
8
at the second falling edge of
LCAS or UCAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Normalize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 512 row addresses at the same column address by using CBR refresh counter test cycles.
4) Read “0” written in procedure 3) by using normal read cycle and check; after reading “0” and check are completed
(or simultaneously), write “1” to the same addresses by using normal write cycle (or read-modify-write cycle).
5) Read and check data “1” written in procedure 4) by using CBR refresh counter test cycle for all 512 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
t
FRSH
t
FCAS
t
RP
HIGH-Z
HIGH-Z
HIGH-Z
t
CHR
t
CSR
t
CP
t
FCAH
t
ASC
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
DZC
t
OED
t
FCAC
t
OEH
t
OEZ
t
OEA
t
ON
t
DZO
t
FCWD
VALID DATA IN
相關(guān)PDF資料
PDF描述
MB81V4265S-70L CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB81V4265S-70 CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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MB81V4400C-70 CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁(yè)模式動(dòng)態(tài)RAM)
MB81V4405C-60 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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