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參數(shù)資料
| 型號(hào)： | MB86836PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit Embedded Controller |
| 中文描述： | 32-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁(yè)數(shù)： | 10/82頁(yè) |
| 文件大?。?/td> | 1373K |
| 代理商： | MB86836PMT2 |
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MB86830 Series
10
I
PIN DESCRIPTION
1.
CPU Core Related Pins
Symbol
(Continued)
Pin name
I/O
Function
CLKIN
CLOCK
I
Clock input pin.
The clock regulates external bus operation.The bus AC characteristics
are determined based on the clock.
CLKEXT
EXTERNAL
CLOCK BYPASS
I
External clock select pin.
The “L” level at this pin selects the clock signal generated by the internal
PLL circuit; theC“H” level selects the external clock signal (input through
the CLKIN pin) as it is.Fix this pin usually at the “L” level.
RESET#
SYSTEM RESET
I
Reset input.
The “L” input to this pin initializes the CPU.
CLKSEL0
CLKSEL1
CLKSEL2
INTERNAL
CLOCK SELECT
I
Internal clock setting pins.
These pins are used to set the IU (integer unit) and cache operating
clock frequencies to x1, x2, x3, x4, or x5 of the external clock frequency.
Any other setting is prohibited.
ASISEL
ADDRESS
SPACE IDENTI-
FIERS SELECT
I
ASI select signal
This pin selects the ASI or ADR pin.
Setting this pin to “L” prohibits the “L” input to the AS# pin in the bus
grant state.
On the MB86832, this pin is pulled up with a resistor of about 50 k
.
CTEST#
BTEST#
CTEST
BTEST
I
Test pins.
Fix these pins usually to the “H” level.
ADR<27:2>
or
ADR<23:2>
(MB86833/
835/836)
ADDRESS BUS
I/O
Address pin.
The ADR<27:2>pin (ADR<23:2>pin on the MB86833/835/836)handles
the signal for identifying an instruction address or data address.For us-
ing the 8/16-bit bus width, ADR<1> and ADR<0> are output multiplexed
with BE2# and BE3#, respectively.This pin remains enabled during the
bus cycle; the value output during the idle cycle is not guaranteed.
In the bus grant state, the pin serves as an input used, e.g., by the CS
generator circuit (while the “L” input to the AS# pin is prohibited with the
ASISEL pin at the “L” level) and ADR<31:28> (ADR<31:24> on the
MB86833/835/836) is handled internally as 0.
CLKSEL2
CLKSEL1
CLKSEL0
Internal clock
×
1
×
2
3
×
4
×
5
H
L
L
H
L
H
H
H
L
H
H
H
L
H
H
ASISEL
MB86832/834
ASI<3:0>/ADR<28:31>
MB86833/835/836
ASI<3:0>/ADR<24:27>
L
ADR<28:31>
ADR<24:27>
H
ASI<3:0>
ASI<3:0>
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