- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377894 > MB86836PMT2 (FUJITSU LTD) 32-bit Embedded Controller PDF資料下載
參數(shù)資料
| 型號： | MB86836PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit Embedded Controller |
| 中文描述： | 32-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 55/82頁 |
| 文件大小： | 1373K |
| 代理商： | MB86836PMT2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
MB86830 Series
55
(7)On-chip interrupt controller
The on-chip interrupt controller accepts interrupt inputs through eight channels, allowing a trigger mode to be set
independently for each of the channels. The interrupt request accepted according to the trigger mode is encoded
and output to the processor.
(8)Multiplier circuit
The MB86830 series incorporates a multiplier circuit which can be selectively set to an operating clock frequency
of x1, x2, x3, x4,or x5 of the external clock frequency, allowing the processor to run at high speed.
(9) Instruction set
The MB86830 series supports high-speed integer multiply instructions which are executed in five, three, and two
cycles respectively for 32-, 16-, and 8-bit multiplications. The integer divide step instruction is near 10 times faster
in divide time than the previous SPARC implementation. The scan instruction supports the function for detecting
1 or 0 at the MSB in a word in a single cycle.
2.
The CPU core of the MB86830 series is a high-performance version implemented by full custom design of the
SPARC architecture. The CPU core contains a compact circuitry for integrating peripheral circuits, designed to be
customizable to a variety of applications. The CPU core consists of three function units: instruction, address, and
execution blocks (see “Integer operation unit internal block diagram”).
The role of five execution stages for instruction pipelining is to decode all instructions and generate control signals
for other blocks. The five pipelined stages are the fetch (F), decode (D), execute (E), memory (M), and write back
(W) stages. The instruction memory returns an instruction addressed at stage (F), the register file returns an op-
erand addressed at stage (D), the ALU perform calculation to obtain the result at stage(E), the external memory is
addressed at stage(M), and the register file is written back at stage (W).
CPU
相關PDF資料 |
PDF描述 |
|---|---|
| MB86941PFV | Peripheral LSI for SPARClite |
| MB86941 | Peripheral LSI for SPARClite |
| MB86942 | Peripheral LSI for SPARClite |
| MB86942PFV | Peripheral LSI for SPARClite |
| MB86960 | NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
發(fā)布緊急采購，3分鐘左右您將得到回復。