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| 型號(hào)： | MB89P195APF-201 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4.2 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 8.60 X 17.75 MM, 1.27 MM PITCH, PLASTIC, SOP-28 |
| 文件頁(yè)數(shù)： | 40/256頁(yè) |
| 文件大小： | 1811K |
| 代理商： | MB89P195APF-201 |
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7-14 Chapter 7 8-/16-bit Timer/Counter
MB89190/190A series
7.4 Registers for 8-/16-bit Timer/Counter
7.4.4 Timer 2 Data Register (T2DR)
The timer 2 data register (T2DR) is used to set the 8-bit mode timer 2, or 16-bit
mode upper 8-bit interval timer value (when the interval timer function is
working), or the counter value (when the counter function is working), and to read
the counter value.
T Timer 2 data register (T2DR)
The value set in this register is compared to the counter value. When this register is read, the current
counter value is read. The setting of this register cannot be read.
Figure 7.4.4 shows the bit configuration of the timer 2 data register.
Fig. 7.4.4 Timer 2 Data Register (T2DR)
In 8-bit mode (timer 2)
The value of this register is compared to the timer 2 counter value. When the interval timer function is
working, the interval time value is set. When the counter function is working, the count value to be
detected is set. The T2DR register is reset (loaded) to the comparate data latch when the count
operation starts and when a match to the counter value is detected. When a value is written to the
T2DR register during operation of the counter, it becomes valid from the next cycle (after detection of
a match).
Remark: The T2DR register setting during the interval timer operation can be calculated from the
following expression. However, the instruction cycle is the original oscillation divided by 4
(4/Fc).
T2DR register value = interval time/(count clock cycle
× instruction cycle) 1
In 16-bit mode
The value of this register is compared to the upper 8-bit count value of the 16-bit timer. When the
interval timer function is working, the interval timer upper 8 bits are set. When the counter function is
working, the upper 8 bits of the count value to be detected are set. The T2DR register is loaded to the
upper 8 bits of the comparate data latch when the count operation starts and when a match to the 16-
bit counter value is detected. When a value is written to the T2DR register during operation of the 16-
bit counter, it becomes valid after detection of a match. The count operation in the 16-bit mode is
controlled using the timer 1 control register (T1CR).
Remark:
The setting of the T1DR and T2DR registers during the interval function operation can be
calculated from the following expression.
However, the instruction cycle is the original
oscillation divided by 4 (4/Fc).
16-bit data value = interval time/(count clock cycle
× instruction cycle) 1
The 16-bit data value upper 8 bits are set in the T2DR register, and the lower 8 bits are set in
the T1DR register.
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Initial value
001AH
XXXXXXXXB
R/W
:
Read and Write
X:
Undefined
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB89P195AP-201 | 8-BIT, OTPROM, 4.2 MHz, MICROCONTROLLER, PDIP28 |
| MB89P195PF-100 | 8-BIT, OTPROM, 4.2 MHz, MICROCONTROLLER, PDSO28 |
| MB89P558A-201PFV | 8-BIT, OTPROM, 12.5 MHz, MICROCONTROLLER, PQFP100 |
| MB89P558A-201PFT | 8-BIT, OTPROM, 12.5 MHz, MICROCONTROLLER, PQFP100 |
| MB89P558A-202PFV | 8-BIT, OTPROM, 12.5 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB89P195P-101 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P195PF-101 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P1A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P475 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89P475-101PFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
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