參數(shù)資料
型號: MB89P965PFV
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 111/278頁
文件大小: 1847K
代理商: MB89P965PFV
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁當(dāng)前第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁
MB89960 series
CHAPTER 10 8-Bit Serial I/O
177
10
Table 10.3.1 Serial Mode Register (SMR) Bits
NO.
Bit
Function
bit7
SIOF:
Interrupt request flag bit
This bit is set to “1” when the serial output operation has output 8 bits of serial
data or the serial input operation has input 8 bits of serial data. An interrupt
request is output when both this bit and the interrupt request enable bit (SIOE)
are “1”.
Writing “0” clears the bit. Writing “1” has no effect and does not change the bit
value.
bit6
SIOE:
Interrupt request enable
bit
Enables or disables output of interrupt requests to the CPU. An interrupt request is
output when both this bit and the interrupt request flag bit (SIOF) are “1”.
bit5
SCKE:
Shift clock output
enable bit
Controls input and output of the shift clock.
The P30/SCK pin operates as the shift clock input pin when this bit is “0” and as
the shift clock output pin when the bit is “1”.
Cautions: Set the P30/SCK pin as an input port in the port direction register
(DDR3: bit 0= “0”) when the SCK pin is set to operate as the shift
clock input pin (SCKE = “0”). Also, select external shift clock
operation using the shift clock selection bits (CKS1, CKS0 = 11B)
When set as the shift clock output pin (SCKE = “1”), select internal
shift clock operation (CKS1, CKS0 = other than 11B).
Notes: When the SCK pin is set to operate as the shift clock output (SCKE =
“1”), the pin operates as an output even if the port direction register
corresponding to the general-purpose port (P30) is set to input (DDR3:
bit 0= “0”).
Set to shift clock input operation (SCKE = “0”) when using the pin as a
general-purpose port (P30).
bit4
SOE:
Serial data output
enable bit
The P31/SO pin operates as a general-purpose port (P31) when this bit is set to
“0” and as the serial data output pin (SO) when set to “1”.
Note: If serial data output is selected (SOE = “1”), the SO pin operates as an
output even if the port direction register corresponding to the general-
purpose port (P31) is set to input (DDR3: bit 1= “0”).
bit3
bit2
CKS1, CKS0:
Shift clock selection bits
Selects the shift clock from one external and three internal shift clocks.
Setting the bits to other than “11B” selects an internal shift clock. In this case,
the shift clock is output from the SCK pin if the shift clock output enable bit
(SCKE) is “1”.
Setting the bits to “11B” selects the external shift clock. This inputs the shift
clock from the SCK pin if shift clock input is enabled (SCKE = “0” and DDR3: bit
0= “0”).
bit1
BDS:
Transfer direction
selection bit
This bit selects whether serial data is transferred with the least significant bit first
(LSB-first, BDS = “0”) or the most significant bit first (MSB-first, BDS = “1”).
Caution: As bits are set in the appropriate order when writing to or reading from
serial data register (SDR), modifying this bit does not apply to any data
already set in the SDR register.
bit0
SST:
Serial I/O transfer start
bit
Controls serial I/O transfer start and transfer enable. This bit can also be used
to determine whether transfer has completed.
Writing “1” to this bit when an internal shift clock is selected (CKS1, CKS0 =
other than “11B”) clears the shift clock counter and starts data transfer.
Writing “1” to this bit when the external shift clock is selected (CKS1, CKS0 =
“11B”) enables data transfer, clears the shift clock counter, and sets serial I/O to
wait for input of the external shift clock.
This bit is cleared to “0” and the SIOF bit set to “1” when transfer completes.
Writing “0” to this bit while transfer is in progress (SST = “1”) aborts the transfer.
After aborting a transfer, data must be set again to the SDR register for data
output and transfer restarted (the shift clock counter cleared) for data input.
相關(guān)PDF資料
PDF描述
MB89F202RAPFV-GE1 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDSO34
MB89F202YPFV 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDSO34
MB89N202-PSH 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDIP32
MB89F202-PSH 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDIP32
MB89202-PSH 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PDIP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB89P980 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89P985 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89P985-PFM-101 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89P985-PFM-201 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller
MB89P985PFV-101 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller