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參數(shù)資料
| 型號： | MB89P965PFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 261/278頁 |
| 文件大?。?/td> | 1847K |
| 代理商： | MB89P965PFV |
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MB89960 series
CHAPTER 3 CPU
61
3
s Sleep Mode Operation
q Changing to sleep mode
Sleep mode halts the CPU operating clock. The CPU halts while maintaining all register
contents, RAM contents, and pin states at their values immediately prior to entering sleep mode.
However, peripheral functions continue to operate.
Writing a “1” to the SLP bit of the STBC switches to the sleep mode. If an interrupt request is
present when “1” is written to the SLP bit, the write to the SLP bit is ignored, the CPU does not
change to sleep mode, and instruction execution continues. (The CPU does not change to sleep
mode after completing interrupt processing.)
q Cancelling sleep mode
A reset or an interrupt from a peripheral function cancels sleep mode.
If a reset occurs during sleep mode, the CPU is switched to the reset state and the sleep mode
is cancelled. Refer to section 3.5.2 for reset sequence.
When an interrupt of level “11” or higher is requested from the peripheral during the sleep mode,
the sleep mode is cancelled. When the I and IL flag bits are set to accept an interrupt after
cancelling the sleep mode, the CPU executes the interrupt processing. When they are set to
ignore, the CPU executes the interrupt processing from the next instruction.
s Stop Mode Operation
q Changing to stop mode
The stop mode is different when the main clock is operating and when the sub clock is operating:
When the main clock is operating, the stop mode stops the main clock but the sub
clock does not stop. All function except the chip clock function stop.
When the sub clock is operating, both the main and the sub clock stop. All chip
function stop.
For MB89965, the internal 3V voltage regulator is in stanby in stop mode to reduce power
consumption.Therefore all the peripherals with analog circuits (A/D convertor) must be disabled
before entering stop mode.
All register and RAM contents at their values immediately prior to entering stop mode are
preserved. Accordingly, data can be maintained with minimum power consumption.
Writing a “1” to the STP bit of the STBC switches to the stop mode. During the stop mode,
whether the I/O and output pins are set to the previous or high-impedence state can be
controlled by the SPL bit of the STBC. If an interrupt is requested when a 1 is being written in
the STP bit, execution of the instruction continues without switching to the stop mode.
q Cancelling stop mode
A reset or an external interrupt cancels stop mode.
When a reset signal is inputted during the sleep mode, the CPU is switched to the reset state,
and the stop mode is released. When an interrupt of level “11” or higher is requested from the
external interrupt circuit during the stop mode, stop mode is released.
After oscillation stabilization time ( plus regulator recovery time for MB89965, refer to section
3.6.2) since the stop mode was released has escaped, when the I-flag and the IL bits are set to
accept an interrupt, the CPU executes the interrupt processing. When they are set to ignore, the
CPU executes the interrupt processing from the next instruction.
Three types of the oscillation stabilization time of the main clock can be selected by the WT1
and WT0 bits. The oscillation stabilization time of the sub clock is fixed (215/fcl, fcl:sub clock
frequency).
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