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參數(shù)資料
| 型號(hào)： | MB89P965PFV |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 262/278頁(yè) |
| 文件大?。?/td> | 1847K |
| 代理商： | MB89P965PFV |
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62
CHAPTER 3 CPU
MB89960 series
If the stop mode is released by the reset, the CPU switched to the oscillation stabilization wait
state. Therefore the reset sequence is executed only after the oscillation stabilization time has
elapsed. The oscillation stabilization time of the main clock selected by WT1 and WT0 bits is
used as the oscillation stabilization time, plus regulator recovery time for MB89965
s Clock Mode Operation
q Changing to clock mode
The clock mode stops all functions except the clock prescaler, external interrupt, and wake-up
interrupt. The contents of the registers and RAM are saved in this mode, so data can be
preserved with the lowest power consumption.
Writing a “1” to the TMD bit of the STBC switches to the clock mode. If a “1” is set in the SCS bit
of the SYCC, the writing action is ignored. If an interrupt is requested when a “1” is writing to the
TMD bit, execution of the instruction continues without switching to the clock mode. While in the
clock mode, the SPL bit in the STBC can control whether the I/O and output pins are set to their
previous value or set to high-impendence state.
q Cancelling clock mode
The clock mode is cancelled by a external reset or by a interrupt. When the reset is inputted
during the clock mode, the CPU is switched to the reset state and the clock mode is released.
When an interrupt higher than level “11” is requested from the resource circuit during the clock
mode, the clock mode is also cancelled.
When the I and IL flags are set to accept an interrupt after release, the CPU executes the
interrupt processing. When they are set to ignore an interrupt, the CPU executes the interrupt
processing from the next instruction before entering the clock mode.
If the clock mode is released by the reset, the CPU switched to the oscillation stabilization wait
state. Therefore, the reset sequence is executed only after the oscillation stabilization time (
regulator recovery time for MB89965) has elapsed. Refer to section 3.5.2 for the reset
sequence. The oscillation stabilization time of the main clock selected by the WT1 and WT0 bits
of the SYCC is used as the oscillation stabilization time.
s Setting standby modes
Note:Writing “1” at bit 6 and bit 3 of the STBC register in the stop mode causes a
malfunction. Always write 0. (Avoid three settings as noted in the above table).
When the mode is switched from sub clock to main clock, do not set the stop,
sleep and other low-power consumption modes. If the SCS bit of the SYCC
register is written from “0” to “1”, set each low-power consumption mode after
the SCM bit of the SYC register is set to “1”.
Table 3.7a Low power consumption mode
STBC register
Mode
STP (bit 7)
SLP (bit 6) TMD (bit 3)
0
Normal
00
1
Clock
0
1
0
Sleep
10
0
Stop
1
-
Prohibited
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