![](http://datasheet.mmic.net.cn/120000/MB90F395HAPMT_datasheet_3559137/MB90F395HAPMT_20.png)
20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.3.2 Interrupt Request Register 1
Fig. 8.3.3 Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
BNameFunctions
After reset RW
Interrupt Request Register 1
0
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
(TM1R)
1Timer 2 interrupt
request bit
(TM2R)
2Timer 3 interrupt
request bit
(TM3R)
3
Timer 4 interrupt
request bit
(TM4R)
4OSD interrupt request
bit
(OSDR)
5VSYNC interrupt
request bit
(VSCR)
6
INT3 external interrupt
request bit
(VSCR)
7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
V
0
V
0
V
0
V
0
V
0
V
0
V
V: “0” can be set by software, but “1” cannot be set.
—
R
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
b7b6 b5 b4b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address 00FD
BNameFunctions
After reset RW
Interrupt Request Register 2
0
INT1 external interrupt
request bit (INIR)
0 : No interrupt request issued
1 : Interrupt request issued
1
Data slicer interrupt
request bit (DSR)
2
Serial I/O interrupt
request bit (S1R)
3
4
INT2 external interrupt
request bit (IN2R)
5
7Fix this bit to “0.”
0
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
V: “0” can be set by software, but “1” cannot be set.
0
V
0
V
0
V
0
V
0 : No interrupt request issued
1 : Interrupt request issued
16
]
R
R V
R
R V
R W
f(XIN)/4096 interrupt
request bit (CKR)
0 : No interrupt request issued
1 : Interrupt request issued
Multi-master I2C-BUS
interrupt request bit (IICR)
0 : No interrupt request issued
1 : Interrupt request issued
6
Timer 5 6 interrupt
request bit (TM56R)
0 : No interrupt request issued
1 : Interrupt request issued
0
V
R