參數資料
型號： MB90F395HAPMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數： 47/72頁
文件大?。?/td> 1734K
代理商： MB90F395HAPMT
51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Figures 8.10.4 and 8.10.5 the data slicer control registers.
Fig. 8.10.4 Data Slicer Control Register 1
Fig. 8.10.5 Data Slicer Control Register 2
b7b6b5b4b3b2b1b0
Data slicer control register 1(DSC1) [Address 00E016]
Data Slicer Control Register 1
00
RW
0R W
2Reference clock source
selection bit (DSC12)
0: Video signal
1: HSYNC signal
0R W
0
RW
11
0: Stopped
1: Operating
Data slicer and timing signal
generating circuit control bit (DSC10)
Fix these bits to “0.”
3, 4
00 0
10: F2
1: F1
Selection bit of data slice reference
voltage generating field (DSC11)
Fix these bits to “1.”
5, 6
Definition of fields 1 (F1) and 2 (F2)
Hsep
Vsep
F1:
Hsep
Vsep
F2:
B
After reset R W
NameFunctions
0R W
Fix this bit to “0.”
7
b7b6b5b4b3b2b1b0
Data slicer control register 2 (DSC2) [Address 00E116]
R W
Data Slicer Control Register 2
0Indeterminate R—
1
0R W
IndeterminateR —
01
0: Data is not latched yet
and a clock-run-in is not
determined.
1: Data is latched and a
clock-run-in is determined.
Caption data latch
completion flag 1
(DSC20)
Fix this bit to “1.”
2Read-only
Test bit
30: F2
1: F1
Field determination
flag(DSC23)
40: Method (1)
1: Method (2)
Vertical synchronous signal
(Vsep) generating method
selection bit (DSC24)
0R W
50: Match
1: Mismatch
V-pulse shape
determination flag (DSC25)
IndeterminateR —
6
0
RW
Fix this bit to “o.”
B
After reset
Functions
Name
Definition of fields 1 (F1) and 2 (F2)
Hsep
Vsep
F1:
Hsep
Vsep
F2:
R—
7
Read-only
Test bit
Indeterminate
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