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參數(shù)資料
| 型號： | MB90F395HAPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 70/72頁 |
| 文件大?。?/td> | 1734K |
| 代理商： | MB90F395HAPMT |
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72
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.14 Relation between Field Determination Flag and Display Font
Both HSYNC signal and VSYNC signal are negative-polarity input
Field
Even
Odd
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
0 (T2 > T1)
1 (T3 < T2)
0
1
0
1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 16) to “0.”
T2
T3
OSD ROM font configuration diagram
Dot line 0
Dot line 1
Odd
Dot line 0
Dot line 1
(n |1) field
(Odd-numbered)
T1
0.25 to 0.50[ s] at
f(XIN)
8 MHz
CC mode
13
57
9
11
13
15
1
3
5
7
9
11
13
15
17
19
21
23
25
26
24
22
20
18
16
14
12
10
8
6
4
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
17
19
20
18
16
14
12
10
8
6
4
2
13
5
7
9
11
13
15
2
4
6
8
10
12
14
16
OSD mode
HSYNC
VSYNC and
VSYNC
control
signal
in microcom-
puter
Upper :
VSYNC signal
Lower :
VSYNC control
signal in
micro-
computer
(n) field
(Even-numbered)
(n {1) field
(Odd-numbered)
When the display dot line selection bit is “0,”
the “
” font is displayed at even field, the
“
” font is displayed at odd field. Bit 6 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in
the microcomputer.
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