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參數(shù)資料
| 型號(hào)： | MB90F395HAPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 65/72頁 |
| 文件大小： | 1734K |
| 代理商： | MB90F395HAPMT |
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68
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
The horizontal display start position is common to all blocks, and can
be set in 128 steps (where 1 step is 4TOSC, TOSC being the OSD
oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the hori-
zontal position register (address 00D116). The horizontal position reg-
ister is shown in Figure 8.11.8.
Fig. 8.11.8 Horizontal Position Register
Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs
between the horizontal display start position set by the horizontal
position register and the most left dot of the 1st block. Accordingly,
when 2 blocks have different pre-divide ratios, their horizontal dis-
play start position will not match.
2 : The horizontal start position is based on the OSD clock source cycle
selected for each block. Accordingly, when 2 blocks have different
OSD clock source cycles, their horizontal display start position will
not match.
3 : When setting “0016” to the horizontal position register, it needs ap-
proximately 62TOSC (= Tdef) interval from a rising edge (when nega-
tive polarity is selected) of HSYNC signal to the horizontal display start
position.
Fig. 8.11.9 Notes on Horizontal Display Start Position
4TOSC’ ! N
4TOSC ! N
HSYNC
1TC
Note 1
Note 2
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
Tdef
Tdef’
N: Value of horizontal position register (decimal notation)
1TC : OSD clock cycle divided in pre-divide circuit
TOSC : OSD oscillation cycle
Tdef
: 62 TOSC
b7 b6 b5 b4 b3 b2 b1 b0
Horizontal position register (HP) [Address 00D1 16]
B
Name
Horizontal Position Register
7
Horizontal display start
position control bits
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Functions
After reset R W
Horizontal display start positions
128 steps (0016 to 7F16)
(1 step is 4TOSC)
0
RW
R—
0
to
6
Note: The setting value synchronizes with the V SYNC.
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