127
MB90570 Series
Table 21
Other Control Instructions (Byte/Word/Long Word) [28 Instructions]
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3
× (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3
× (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count
× (c), or push count × (c)
*5: Pop count or push count.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
POPW A
POPW AH
POPW PS
POPW rlst
JCTX
@A
AND CCR, #imm8
OR
CCR, #imm8
MOV RP, #imm8
MOV ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
ADDSP #imm8
ADDSP #imm16
MOV
A, brgl
MOV
brg2, A
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
2
1
2
1
2
2+
2
2+
2
3
2
1
4
*3
3
4
*2
14
3
2
3
2+ (a)
1
1+ (a)
3
*1
1
0
*5
0
*5
0
1
0
(c)
*4
(c)
*4
6
× (c)
0
word (SP)
← (SP) –2, ((SP)) ← (A)
word (SP)
← (SP) –2, ((SP)) ← (AH)
word (SP)
← (SP) –2, ((SP)) ← (PS)
(SP)
← (SP) –2n, ((SP)) ← (rlst)
word (A)
← ((SP)), (SP) ← (SP) +2
word (AH)
← ((SP)), (SP) ← (SP) +2
word (PS)
← ((SP)), (SP) ← (SP) +2
(rlst)
← ((SP)), (SP) ← (SP) +2n
Context switch instruction
byte (CCR)
← (CCR) and imm8
byte (CCR)
← (CCR) or imm8
byte (RP)
←imm8
byte (ILM)
←imm8
word (RWi)
←ear
word (RWi)
←eam
word(A)
←ear
word (A)
←eam
word (SP)
← (SP) +ext (imm8)
word (SP)
← (SP) +imm16
byte (A)
← (brgl)
byte (brg2)
← (A)
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
Z
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–