
MB90570 Series
38
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
(2) Block Diagram
. . . . . . . . . . . .
Timebase timer control register (TBTC)
RESV
—
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 0
—
R/W
W
R/W
(WDTC)
Initial value
1--00100B
Address
0000A9H
—
TBIE
TBOF
TBR
TBC1
TBC0
R/W : Readable and writable
W : Write only
— : Unused
RESV : Reserved bit
. . .
To 8/16-bit PPG timer
Timebase timer counter
Divided-by-2
of HCLK
Power-on reset
Start stop mode
CKSCR : MCS = 1
→0*1
Counter
clear circuit
Interval
timer selector
Clear TBOF
Set TBOF
Timebase timer control register
(TBTC)
Timebase timer
interrupt signal
#34*2
OF: Overflow
HCLK: Oscillation clock
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt signal
RESV
——
TBIE
TBR
TBOF
TBC1 TBC0
To oscillation stabilization
time selector of clock control block
To watchdog timer
OF
× 21 × 22 × 23
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218