- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69021 > MB90F57APMT (FUJITSU LTD) 16-BIT, FLASH, MICROCONTROLLER, PQFP120 PDF資料下載
參數(shù)資料
| 型號： | MB90F57APMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 59/133頁 |
| 文件大?。?/td> | 2509K |
| 代理商： | MB90F57APMT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
31
MB90570 Series
s PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus
pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode.
Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR
register for output, however, values of bits configured by the DDR register as inputs are changed because
input values to the pins are written into the output latch. To avoid this situation, configure the pins by the
DDR register as output after writing output data to the PDR register when configuring the bit used as
input as outputs.
Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90F897YPMT | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| MB90F922NCSPMC | MICROCONTROLLER, PQFP120 |
| MB90F922NCPMC | MICROCONTROLLER, PQFP120 |
| MB90F924NCPMC | MICROCONTROLLER, PQFP120 |
| MB90F946APF | MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90F583BPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F583BPMC-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F583CAPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F591GPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F594APFR-GE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。