參數(shù)資料
型號： MB90F57APMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁數(shù)： 74/133頁
文件大小： 2509K
代理商： MB90F57APMT
45
MB90570 Series
(1) 16-bit free run Timer
The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler
register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and
output compare (OCU).
A counter operation clock can be selected from four internal clocks (
φ/4, φ/16, φ/32 and φ/64).
An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0.
(Compare match requires mode setup.)
The counter value can be initialized to “0000H” by a reset, software clear or compare match with OCU compare
register 0.
Register Configuration
Block Diagram
free run timer data register (TCDT)
bit 15
bit 8
free run timer control status register (TCCS)
IVF
RESV
(Disabled)
R/W
bit 7
bit 6
bit 5
bit 4
Initial value
00000000B
STOP
IVFE
CLR
MODE
CLK0
CLK1
.............
bit 3
bit 2
bit 1
bit 0
R/W :
Readable and writable
RESV : Reserved bit
Address
000058H
Address
000056H
000057H
bit 15
Initial value
00000000B
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
T15 T14 T13 T12 T11 T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
free run timer data register (TCDT)
16-bit free run timer
interrupt request
#20*
* : Interrupt number
φ: Machine clock frequency
OF : Overflow
2
OF
free run timer
control status register
(TCCS)
φ
16-bit counter
STOP
CLK
CLR
Communications
prescaler register
RESV
IVF
IVFE STOP MODE CLR
CLK1 CLK0
OCU compare register ch.0
match signal
Internal
data
bus
Count value output
to ICO and OCU
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