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參數(shù)資料
| 型號： | MB90F897SPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125 |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 33/78頁 |
| 文件大?。?/td> | 746K |
| 代理商： | MB90F897SPMT |
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MB90895 Series
33
4.
16-bit Input/Output Timer
The 16-bit input/output timer is a compound module composed of 16-bit free-run timer, (1 unit) and input capture
(2 units, 4 input pins). The timer, using the 16-bit free-run timer as a basis, enables measurement of clock cycle
of an input signal and its pulse width.
Configuration of 16-bit input/output timer
The 16-bit input/output timer is composed of the following modules:
16-bit free-run timer (1 unit)
Input capture (2 units, 2 input pins per unit)
Functions of 16-bit input/output timer
(1) Functions of 16-bit free-run timer
The 16-bit free-run timer is composed of 16-bit up counter, timer counter control status register, and prescaler.
The 16-bit up counter increments in synchronization with dividing ratio of machine clock.
Count clock is set among 8 types of machine clock dividing rates.
Count clock :
φ
,
φ
/2,
φ
/4,
φ
/8,
φ
/16,
φ
/32,
φ
/64,
φ
/128
Generation of interrupt is allowed by counter value overflow.
Activation of expanded intelligent I/O service (EI
2
OS) is allowed by interrupt generation.
Counter value of 16-bit free-run timer is cleared to “0000
H
” by either resetting or software-clearing with timer
count clear bit (TCCS: CLR).
Counter value of 16-bit free-run timer is output to input capture, which is available as base time for capture
operation.
(2) Functions of input capture
The input capture, upon detecting an edge of a signal input to the input pin from external device, stores a counter
value of 16-bit free-run timer at the time of detection into the input capture data register. The function includes
the input capture data registers corresponding to four input pins, input capture control status register, and edge
detection circuit.
Rising edge, falling edge, and both edges are selectable for detection.
Generating interrupt on CPU is allowed by detecting an edge of input signal.
Expanded intelligent I/O service (EI
2
OS) is activated by interrupt generation.
The four input capture input pins and input capture data registers allows monitoring of a maximum of four events.
16-bit input/output timer block diagram
Internal data bus
Input capture
Special-
purpose bus
16-bit free-run
timer
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