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參數(shù)資料
| 型號： | MB90F897SPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125 |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 43/78頁 |
| 文件大?。?/td> | 746K |
| 代理商： | MB90F897SPMT |
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MB90895 Series
43
8.
Delay Interrupt Generation Module Outline
The delay interrupt generation module is a module that generates interrupts for switching tasks. Generation of
a hardware interrupt request is performed by software.
Delay interrupt generation module outline
Using the delay interrupt generation module, hardware interrupt request is generated and released by software.
Delay interrupt generation module outline
Delay interrupt generation module block diagram
Interrupt request latch
A latch that retains settings on delay interrupt request generation/release register (generation or release of delay
interrupt request).
Delay interrupt request generation/release register (DIRR)
Generates or releases delay interrupt request.
Interrupt number
An interrupt number used in delay interrupt generation module is as follows:
Interrupt number: #42 (2A
H
)
Function and control
Cause of interrupt
Set “1” in R0 bit of delay interrupt request generation/release register (DIRR: R0=1),
generating an interrupt request.
Set “0” in R0 bit of delay interrupt request generation/release register (DIRR: R0=0),
releasing an interrupt request.
Interrupt number
#42 (2A
H
)
Interrupt control
No setting of permission register is provided.
Interrupt flag
Retained in DIRR: R0 bit
EI
2
OS
Not ready for expanded intelligent I/O service.
R0
Internal data bus
Delay interrupt request generation/release
register (DIRR)
: Not defined
S Interrupt request
R Latch
Interrupt
request signal
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