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參數(shù)資料
| 型號： | MB90F897SPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125 |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 38/78頁 |
| 文件大?。?/td> | 746K |
| 代理商： | MB90F897SPMT |
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MB90895 Series
38
6.
Clock Timer Outline
The clock timer is a 15-bit free-run counter that increments in synchronization with sub clock.
Interval time is selectable among 8 choices, and generation of interrupt request is allowed for each interval.
Provides operation clock to the subclock oscillation stabilizing wait timer and watchdog timer.
Always uses subclock as a count clock regardless of settings of clock selection register (CKSCR).
Interval timer function
In the clock timer, a bit corresponding to the interval time overflows (carry-over) when an interval time, which
is specified by interval time selection bit, is reached. Then overflow flag bit is set (WTC: WTOF=1).
If an interrupt by overflow is permitted (WTC: WTIE=1), an interrupt request is generated upon setting an
overflow flag bit.
Interval time of clock timer is selectable among the following 8 choices :
Interval time of clock timer
SCLK: Sub clock frequency
Values in parentheses “( )” are calculation when operating with 8.192 kHz clock.
Sub clock cycle
Interval time
SCLK (122
μ
s)
2
8
/SCLK (31.25 ms)
2
9
/SCLK (62.5 ms)
2
10
/SCLK (125 ms)
2
11
/SCLK (250 ms)
2
12
/SCLK (500 ms)
2
13
/SCLK (1.0 s)
2
14
/SCLK (2.0 s)
2
15
/SCLK (4.0 s)
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