參數(shù)資料
型號(hào): MB91101APF
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 52/99頁
文件大小: 935K
代理商: MB91101APF
MB91101/MB91101A
56
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions.
CPU clock generation (including gear function)
Peripheral clock generation (including gear function)
Reset generation and cause hold
Standby function (including hardware standby)
DMA request prohibit
PLL (multiplier circuit) embedded
Block diagram
Gear control register (GCR)
[Gear control block]
PCTR register
CPU gear
Peripheral
gear
Oscillator
circuit
X0
X1
1/2
PLL
Internal clock
generation
circuit
CPU clock
Internal bus clock
External bus clock
Peripheral
DMA clock
Internal
peripheral clock
[Stop/sleep control block]
Internal
interrupt request
Internal reset
Standby control
register (STCR)
STOP state
SLEEP state
CPU hold request
Internal reset
Reset
generation
F/F
CPU hold enable
HST pin
DMA
request
Power on sel
RST pin
DMA request prohibit
register (PDRR)
[DMA prohibit circuit]
Reset cause register (RSRR)
Timebase timer
Count clock
Watchdog reset
postpone register
[Watchdog control block]
Timebase timer clear
register (CTBR)
Watchdog reset generation
postpone register (WPR)
R-bus
Selection
circuit
[Reset cause circuit]
Status
transition
control circuit
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