參數(shù)資料
型號(hào)： MB91101APF
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 77/99頁
文件大?。?/td> 935K
代理商： MB91101APF
MB91101/MB91101A
79
(8) Normal DRAM Mode Read/Write Cycle
(VCC5 = 5.0 V
±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0
°C to +70°C)
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
*2: Rating at a gear cycle of
× 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (3 – n/2)
× tCYC – 16
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min
Max
RAS delay time
tCLRAH
CLK, RAS0, RAS1
—
—6
ns
tCHRAL
CLK, RAS0, RAS1
—
6
ns
CAS delay time
tCLCASL
CLK, CS0H, CS0L,
CS1H, CS1L
—6
ns
tCLCASH
CLK, CS0H, CS0L,
CS1H, CS1L
—6
ns
ROW address delay time
tCHRAV
CLK,
A24 to A00
—15
ns
COLUMN address delay
time
tCHCAV
CLK,
A24 to A00
—15
ns
DW delay time
tCHDWL
CLK, DW0, DW1
—15
ns
tCHDWH
CLK, DW0, DW1
—15
ns
Output data delay time
tCHDV1
CLK,
D31 to D16
—15
ns
RAS
↓→ valid data input
time
tRLDV
RAS0, RAS1,
D31 to D16
—
5/2
× tCYC
– 16
ns
*1
*2
CAS
↓→ valid data input
time
tCLDV
CS0H, CS0L, CS1H,
CS1L, D31 to D16
—tCYC – 17
ns
*1
CAS
↑→ data hold time
tCADH
CS0H, CS0L, CS1H,
CS1L, D31 to D16
0—
ns
相關(guān)PDF資料
PDF描述
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