參數(shù)資料
型號(hào): MB91101APF
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 65/99頁(yè)
文件大?。?/td> 935K
代理商: MB91101APF
MB91101/MB91101A
68
(1) Clock Timing Rating
(VCC5 = 5.0 V
±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0
°C to +70°C)
*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock
multiplication system.
*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and
a 1/8 gear.
*3: Values when using the doubler and CPU operation at 50 MHz.
Parameter
Symbol
Pin
name
Condition
Value
Unit
Remarks
Min
Max
Clock frequency
fC
X0, X1
When using PLL
10
12.5
MHz
fC
X0, X1
Self-oscillation
(divide-by-2 input)
10
25
MHz
fC
X0, X1
External clock
(divide-by-2 input)
10
25
MHz
Clock cycle time
tC
X0, X1
When using PLL
80
100
ns
tC
X0, X1
40
100
ns
Frequency shift ratio
(when locked)
f
When using PLL
5
%
*1
Input clock pulse width
PWH,
PWL
X0, X1
25
ns
Input to X0
only, when
using 5 V
power supply
PWH,
PWL
X0, X1
10
ns
Input to X0,
X1
Input clock rising/falling time
tCR,
tCF
X0, X1
8
ns
(tCR + tCF)
Internal operating clock
frequency
fCP
CPU system
0.625*2
50
MHz
fCPB
Bus system
0.625*2
25*3
MHz
fCPP
Peripheral system
0.625*2
25
MHz
Internal operating clock
cycle time
tCP
CPU system
20
1600*2
ns
tCPB
Bus system
40*3
1600*2
ns
tCPP
Peripheral system
40
1600*2
ns
f =
× 100 (%)
|
α|
f0
Center frequency f 0
+
α
α
+
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