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參數(shù)資料
| 型號： | MB91101APF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 67/99頁 |
| 文件大?。?/td> | 935K |
| 代理商： | MB91101APF |
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MB91101/MB91101A
7
*1: FPT-100P-M05
*2: FPT-100P-M06
(Continued)
Pin no.
Pin name
Circuit
type
Description
LQFP*1
QFP*2
11
14
CS0
L
Chip select 0 output (“L” active)
10
13
CS1
F
Chip select 1 output (“L” active)
PA1
Can be configured as a port when CS1 is not used.
912
CS2
F
Chip select 2 output (“L” active)
PA2
Can be configured as a port when CS2 is not used.
811
CS3
F
Chip select 3 output (“L” active)
PA3
Can be configured as a port when CS3 and EOP1 are not used.
EOP1
EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is en-
abled.
710
CS4
F
Chip select 4 output (“L” active)
PA4
Can be configured as a port when CS4 is not used.
69
CS5
F
Chip select 5 output (“L” active)
PA5
Can be configured as a port when CS5 is not used.
58
CLK
F
System clock output
Outputs clock signal of external bus operating frequency.
PA6
Can be configured as a port when CLK is not used.
96
99
RAS0
F
RAS output for DRAM bank 0
Refer to the DRAM interface for details.
PB0
Can be configured as a port when RAS0 is not used.
97
100
CS0L
F
CASL output for DRAM bank 0
Refer to the DRAM interface for details.
PB1
Can be configured as a port when CS0L is not used.
98
1
CS0H
F
CASH output for DRAM bank 0
Refer to the DRAM interface for details.
PB2
Can be configured as a port when CS0H is not used.
99
2
DW0
F
WE output for DRAM bank 0 (“L” active)
Refer to the DRAM interface for details.
PB3
Can be configured as a port when DW0 is not used.
100
3
RAS1
F
RAS output for DRAM bank 1
Refer to the DRAM interface for details.
PB4
Can be configured as a port when RAS1 and EOP2 are not
used.
EOP2
DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91101APFR-G-JNE1 | 制造商:FUJITSU 功能描述: |
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