參數(shù)資料
型號： MB91302APFF-G-XXX-BNDE1
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 29/140頁
文件大小： 2841K
代理商： MB91302APFF-G-XXX-BNDE1
MB91301 Series
124
DS07-16502-4E
Pin Status List (External bus : 32 bit bus width)
(Continued)
Pin no.
Port
name
Specified
function
name
Function
name
At initialization (INIT)
Sleep
mode
Stop mode
Bus released
(BGRNT)
Function
name
Initial
value
HIZ
= 0
HIZ
= 1
Bus width
32 bit
Bus width
8 bit
CS shared
CS not
shared
1 to 5
P13 to P17
D11 to D15
P13 to P17
Output Hi-Z
Input ready
P : Previous
state held
F : Output
held or
Hi-Z
P : Previous
state held
F : Output
held or
Hi-Z
Output
Hi-Z/
input 0
fixed
Output Hi-Z
8 to 15
P20 to P27
D16 to D23
P20 to P27
18 to 25
P30 to P37
D24 to D31
28
P80
RDY
P80
Output Hi-Z
Input ready
P : Previous
state held
F : RDY input
Previous
state held
Output
Hi-Z/
input 0
fixed
P : Previous
state held
F : RDY input
P : Previous
state held
F : RDY input
29
P81
BGRNT
P81
P : Previous
state held
F : H output
L output
30
P82
BRQ
P82
P : Previous
state held
F : BRQ input
invalid
BRQ input
31
P83
RD
H output
P : Previous
state held
F : H output
Previous
state held
Output Hi-Z
Previous
state held
32
P84
DQMUU/WR0
33
P85
DQMUL/WR1
P85
F : H output
34
P86
DQMLU/WR2
P86
35
P87
DQMLL/WR3
P87
36
P90
SYSCLK
Asserted
: L output
Negated
: CLK output
P : Previous
state held
F : SYSCLK
output
P : Previous
state held
F : H or L out-
put
Output
Hi-Z/
input 0
fixed
F : CLK
output
F : CLK
output
37
P91
MCLKE
H output
F : L output
F : Output
Hi-Z
Output Hi-Z
H output
38
P92
MCLK
Asserted
: L output
Negated
: CLK output
P : Previous
state held
F : H output
P : Previous
state held
F : H output
F : Output
Hi-Z
Output Hi-Z
F : CLK
output
39
P93
P93
Output Hi-Z
Input ready
Previous
state held
Previous
state held
Output
Hi-Z
Port
Function
Port
Function
40
P94
SRAS/LBA/
AS
P94
Output Hi-Z
Input ready
P : Previous
state held
F : H output
H output
Output
Hi-Z
Output Hi-Z
F : H output
41
P95
SCAS/BAA
P95
Output Hi-Z
Input ready
P : Previous
state held
F : H output
H output
Output
Hi-Z
Output Hi-Z
H output
42
P96
SWE/WR
P96
Output Hi-Z
Input ready
P : Previous
state held
F : SWE
output
Previous
state held
Output
Hi-Z/
input 0
fixed
Output Hi-Z
Previous
state held
45 to 52
P40 to P47
A00 to A07
FF output
P : Previous
state held
F : Address
output
The same as
stated left
Output
Hi-Z/
input 0
fixed
Output Hi-Z
55 to 62
P50 to P57
A08 to A15
64 to 67
P60 to P63
A16 to A19
68
P64
A20/SDA0
A20
69
P65
A21/SCL0
A21
70
P66
A22/SDA1
A22
71
P67
A23/SCL1
A23
76 to 79
AN3 to AN0
input invalid
Previous
state held
input invalid
input
invalid
Previous
state held
Previous
state held
81
PG0
INT0/ICU0
PG0
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
P : Previous
state held
F : Input
ready
P : Output
Hi-Z
F : Input
ready
Normal
operation
Normal
operation
82
PG1
INT1/ICU1
PG1
83
PG2
INT2/ICU2
PG2
84
PG3
INT3/ICU3
PG3
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