參數(shù)資料
型號: MB91302APFF-G-XXX-BNDE1
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 8/140頁
文件大?。?/td> 2841K
代理商: MB91302APFF-G-XXX-BNDE1
MB91301 Series
DS07-16502-4E
105
(4) Normal Bus Access Read/Write Operation
(VCC
= 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
* : When the bus is delayed by automatic wait insertion or RDY input, add (tCYC
× number of wait cycles) to the rated
values.
Parameter
Sym-
bol
Pin name
Condition
Value
Unit Remarks
Min
Max
CS0 to CS7 setup
tCSLCH
SYSCLK,
CS0 to CS7
3
ns
CS0 to CS7 hold
tCHCSH
3tCYC
/ 2 + 4ns
Address setup
tASCH
SYSCLK,
A23 to A00
3
ns
tASWL
WR0 to WR3,
A23 to A00
4
ns
tASRL
RD, A23 to A00
5
ns
Address hold
tCHAX
SYSCLK,
A23 to A00
3tCYC
/ 2 + 4ns
tWHAX
WR0 to WR3,
A23 to A00
tCYC
/ 2 5
ns
tRHAX
RD, A23 to A00
tCYC
/ 2 7
ns
Valid address
Valid data input time
tAVDV
A23 to A00,
D31 to D00
3
/ 2×tCYC
11
ns
*
WR0 to WR3 delay time
tCHWL
SYSCLK, WR,
WR0 to WR3
6ns
WR0 to WR3 delay time
tCHWH
6ns
WR0 to WR3 minimum pulse
width
tWLWH
WR,
WR0 to WR3
tCYC
5
ns
Data setup
→WRx↑
tDSWH
WR,
WR0 to WR3,
D31 to D00
tCYC
ns
WRx
↑→
Data hold time
tWHDX
5
ns
RD delay time
tCHRL
SYSCLK,
RD
6
ns
RD delay time
tCHRH
10
ns
RD
↓→
Valid data input time
tRLDV
RD,
D31 to D00
tCYC
10
ns
*
Data setup
→RD↑ time
tDSRH
10
ns
RD
↑→
Data hold time
tRHDX
0
ns
RD minimum pulse width
tRLRH
RD
tCYC
5
ns
AS setup
tASLCH
SYSCLK,
AS
tCYC
/ 2 6
ns
AS hold
tCHASH
3
ns
UUB/ULB/LUB/LLB set up
tBLCH
SYSCLK, UUB/
ULB/LUB/LLB
tCYC
/ 2 6
ns
UUB/ULB/LUB/LLB hold
tCHBH
3
ns
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