參數資料
型號： MB91302APFF-G-XXX-BNDE1
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數： 32/140頁
文件大?。?/td> 2841K
代理商： MB91302APFF-G-XXX-BNDE1
MB91301 Series
DS07-16502-4E
127
(Continued)
P : General-purpose port selected, F : Specified function selected
Notes :
The bus width is determined after a mode vector fetch.
The bus width at initialization time is 8 bits.
Pin no.
Port
name
Specified
function
name
Function
name
At initialization (INIT)
Sleep
mode
Stop mode
Bus released
(BGRNT)
Function
name
Initial
value
HIZ
= 0HIZ = 1
Bus width
16 bit
Bus width
8 bit
CS
shared
CS not
shared
81
PG0
INT0/ICU0
PG0
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
P : Previous
state held
F : Input
ready
P : Output
Hi-Z
F : Input
ready
Normal
operation
Normal
operation
82
PG1
INT1/ICU1
PG1
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
P : Previous
state held
F : Input
ready
P : Output
Hi-Z
F : Input
ready
Normal
operation
Normal
operation
83
PG2
INT2/ICU2
PG2
84
PG3
INT3/ICU3
PG3
85
PG4
INT4/ATG/
FRCK
PG4
86
PG5
INT5/SIN2
PG5
87
PG6
INT6/SOT2
PG6
88
PG7
INT7/SCK2
PG7
90
PJ0
SIN0
PJ0
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
Previous
state held
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
91
PJ1
SOT0
PJ1
92
PJ2
SCK0
PJ2
93
PJ3
SIN1
PJ3
94
PJ4
SOT1
PJ4
95
PJ5
SCK1
PJ5
96
PJ6
PPG0
PJ6
97
PJ7
TRG0
PJ7
98
PH0
TIN0
PH0
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
Previous
state held
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
99
PH1
TIN1/PPG3
PH1
100
PH2
TIN2/TRG3
PH2
103
PB0
DREQ0
PB0
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
Previous
state held
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
104
PB1
DACK0
PB1
105
PB2
DEOP0
PB2
106
PB3
DREQ1
PB3
107
PB4
DACK1/TRG1
PB4
108
PB5
DEOP1/PPG1
PB5
109
PB6
IOWR
PB6
110
PB7
IORD
PB7
122
PA0
CS0
H output
Output Hi-Z
F : SREN
=
0 : H
output,
SREN
=
1 : Out-
put Hi-Z
F : SREN
=
0 : H
output,
SREN
=
1 : Out-
put Hi-Z
123
PA1
CS1
124
PA2
CS2
125
PA3
CS3
126
PA4
CS4/TRG2
CS4
127
PA5
CS5/PPG2
CS5
128
PA6
CS6
129
PA7
CS7
132 to 139 P00 to P07
D00 to D07
P00 to P07
Output Hi-Z
Input ready
P : Previous
state held
F : Output
held or
Hi-Z
P : Previous
state held
F : Output
held or
Hi-Z
Output
Hi-Z/input 0
fixed
Output Hi-Z Output Hi-Z
142 to 144 P10 to P12
D08 to D10
P10 to P12
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