參數(shù)資料
型號(hào): MBM29DL64DF70TN
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT
中文描述: 4M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝: PLASTIC, TSOP1-48
文件頁數(shù): 24/68頁
文件大?。?/td> 854K
代理商: MBM29DL64DF70TN
MBM29DL64DF
-70
24
Simultaneous Operation Table
* : By writing erase suspend command on the bank address of sector being erased, the erase operation becomes
suspended so that it enables reading from or programming the remaining sectors.
Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists
of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks.
Read Mode
The device has two control functions required to obtain data at the outputs. CE is the power control and used
for a device selection. OE is the output control and used to gate data to the output pins.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins, assuming the
addresses have been stable for at least t
ACC
-t
OE
time. When reading out data without changing addresses after
power-up, it is required to input hardware reset or to change CE pin from “H” to “L”
Standby Mode
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, CMOS standby mode is achieved with CE and RESET input held at V
CC
±
0.3 V. Under
this condition the current consumed is less than 5
μ
A Max. During Embedded Algorithm operation, V
CC
active
current (I
CC2
) is required even when CE
=
“H”. The device can be read with standard access time (t
CE
) from either
of these standby modes.
When using the RESET pin only, CMOS standby mode is achieved with RESET input held at V
SS
±
0.3 V
(CE
=
“H” or “L”) . Under this condition the current consumed is less than 5
μ
A Max. Once the RESET pin is
set high, the device requires t
RH
as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state regardless of OE input.
Automatic Sleep Mode
Automatic sleep mode works to restrain power consumption during read-out of device data. This is useful in
applications such as handy terminal which requires low power consumption.
To activate this mode, the device automatically switches itself to low power mode when the device addresses
remain stable during after 150 ns from data valid. It is not necessary to control CE, WE and OE in this mode. In
this mode the current consumed is typically 1
μ
A (CMOS Level) .
During simultaneous operation, V
CC
active current (I
CC2
) is required.
Since the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device reads the data for changed addresses.
Case
1
2
3
4
5
6
7
Bank 1 Status
Read mode
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
Bank 2 Status
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
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