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參數(shù)資料
| 型號： | MBM29DL64DF70TN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| 中文描述： | 4M X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 34/68頁 |
| 文件大?。?/td> | 854K |
| 代理商： | MBM29DL64DF70TN |
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MBM29DL64DF
-70
34
Hardware Sequence Flags Table
*1 : Successive reads from the erasing or erase-suspend sector causes DQ
2
to toggle.
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ
2
bit.
DQ
7
Data Polling
The device features Data Polling as a method to indicate the host that the Embedded Algorithms are in progress
or completed. During the Embedded Program Algorithm, an attempt to read the device produces reverse data
last written to DQ
7
. Upon completion of the Embedded Program Algorithm, an attempt to read the device produces
true data last written to DQ
7
. During the Embedded Erase Algorithm, an attempt to read the device produces a
“0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read device produces
a “1” on DQ
7
. The flowchart for Data Polling (DQ
7
) is shown in “(3) Data Polling Algorithm” in
I
FLOW CHART.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data polling also works as a flag to indicate whether the device is in erase-suspend
mode. DQ
7
goes from “0” to “1” during erase-suspend mode. Notice that to determine DQ
7
entering erase-
suspend mode, indicate the sector address of sector being erased. Data Polling must be performed at sector
addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ
7
is active for approximately 1
μ
s, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
7
is active for approximately 400
μ
s, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
7
) may change
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ
7
at one instant, and then that byte’s valid data the next. Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if device completes the Embedded Algorithm operation and
DQ
7
has valid data, data outputs on DQ
6
to DQ
0
may still be invalid. The valid data on DQ
7
to DQ
0
is read on
successive read attempts.
Status
DQ
7
DQ
7
0
DQ
6
Toggle
Toggle
DQ
5
0
0
DQ
3
0
1
DQ
2
1
In Progress
Embedded Program Algorithm
Embedded Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Program Suspend Read
(Program Suspended Sector)
Program Suspend Read
(Non-Program Suspended Sector)
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
Toggle *
1
Erase
Suspended
Mode
1
1
0
0
Toggle
Data
Data
Data
Data
Data
DQ
7
Toggle
0
0
1 *
2
Program
Suspended
Mode
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Exceeded
Time Limits
DQ
7
0
Toggle
Toggle
1
1
0
1
1
N/A
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
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