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參數(shù)資料
| 型號： | MBM29F002ST |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器) |
| 中文描述： | 200萬（256K × 8）位快閃記憶體（單5V的電源電壓256K × 8位閃速存儲器） |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 591K |
| 代理商： | MBM29F002ST |
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20
MBM29F002T/002B/002ST/002SB
-70/-90/-12
software should check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
TM
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase
TM
Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode (DQ
2
toggles while
DQ
6
does not). See also Table 7 and Figure 13.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from the erasing sector.
RESET
Hardware Reset
The MBM29F002T/002B/002ST/002SB devices may be reset by driving the RESET pin to V
IL
. The RESET pin
has a pulse requirement and has to be kept low (V
IL
) for at least 500 ns in order to properly reset the internal
state machine. Any operation in the process of being executed will be terminated and the internal state machine
will be reset to the read mode 20
μ
s after the RESET pin is driven low. Furthermore, once the RESET pin goes
high, the device requires an additional 50 ns before it will allow read access. When the RESET pin is low, the
device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If
a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted.
Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 10 for the
timing diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase
TM
Algorithm, there is a possibility that the eraseing sector(s)
cannot be used.
Data Protection
The MBM29F002T/002B/002ST/002SB are designed to offer protection against accidental erasure or
programming caused by spurious system level signals that may exist during power transitions. During power up
the device automatically resets the internal state machine in the read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus
cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F002T-90PD# | 制造商:FUJITSU 功能描述: |
| MBM29F002TC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002TC-55 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002TC-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
| MBM29F002TC-90 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K X 8) BIT |
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