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參數(shù)資料
| 型號： | MBM29F016A-12PFTN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 16M (2M X 8) BIT |
| 中文描述： | 2M X 8 FLASH 5V PROM, 120 ns, PDSO48 |
| 封裝： | PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 458K |
| 代理商： | MBM29F016A-12PFTN |
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18
MBM29F016A
-70/-90/-12
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
Refer to Table 7: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
Notes:
1.These status flags apply when outputs are read from a sector that has been erase-suspended.
2.These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode (DQ
2
toggles while
DQ
6
does not). See also Table 7 and Figure 15.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F016A provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29F016A is placed in an Erase Suspend mode,
the RY/BY output will be high, by means of connecting with a pull-up resistor to V
CC
.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during RESET pulse. Refer to Figure 11 for a detailed timing diagram. The RY/BY pin is pulled
high in standby mode.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read (1)
(Erase-Suspended Sector)
1
1
toggles
Erase Suspend Program
DQ
7
(2)
toggles
1 (2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F016A-12PFTR | 16M (2M X 8) BIT |
| MBM29F016A-70PFTN | 16M (2M X 8) BIT |
| MBM29F016A-70PFTR | 1.65A, 2.7-5.5V Single Hot-Swap IC Hi-Side MOSFET, Fault Report, Act-High Enable 8-PDIP -40 to 85 |
| MBM29F016A-90PFTN | 16M (2M X 8) BIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F016A-12PFTN-X# | 制造商:FUJITSU 功能描述: |
| MBM29F016A-12PFTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT |
| MBM29F016A-70 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M x 8) BIT |
| MBM29F016A-70PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M x 8) BIT |
| MBM29F016A-70PFTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT |
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