參數(shù)資料
型號(hào)： MBM29F080-12
廠商： Fujitsu Limited
英文描述： 8M (1M ×8) BIT Flash Memory(1M ×8 位5V 電源電壓閃速存儲(chǔ)器)
中文描述： 8米（1米× 8）位快閃記憶體（1米× 8位5V的電源電壓閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 14/50頁(yè)
文件大小： 667K
代理商： MBM29F080-12
14
MBM29F080
-90/-12
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-
istics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM pro-
grammers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high voltage
onto the address lines is not generally desirable system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Electronic Signature command sequence into the command
register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of
04H. A read cycle from address XX01H returns the device code D5H. (see Table 3.)
All manufacturer and device codes will exhibit odd parity with the DQ
7
defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02H.
Scanning the sector group addresses (A
17
, A
18
, A
19
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical “1” at
device output DQ
0
for a protected sector group.
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the autoselect command during the operation, execute it after writing read/reset command sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins program-
ming. Upon executing the Embedded Program
TM
Algorithm command sequence, the system is not required to
provide further controls or timings. The device will automatically provide adequate internally generated program
pulses and verify the programmed cell margin.
This automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 7,
Hardware Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by
the system at this particular instance of time. Data Polling must be performed at the memory location which is
being programmed.
Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 15 illustrates the Embedded Programming Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does notrequire the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
相關(guān)PDF資料
PDF描述
MBM29F080-90 8M (1M ×8) BIT Flash Memory(1M ×8 位5V 電源電壓閃速存儲(chǔ)器)
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MBM29F080A Single-Channel Current-Limited Power Distribution Switch 8-MSOP-PowerPAD -40 to 85
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參數(shù)描述
MBM29F080-90PFTN 制造商:FUJITSU 功能描述:
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MBM29F080A-55 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8) BIT
MBM29F080A-55PF 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 8M (1M x 8) BIT
MBM29F080A-55PFTN 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 8M (1M x 8) BIT
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