參數(shù)資料
型號(hào)： MBM29F800B-90
廠(chǎng)商： Fujitsu Limited
英文描述： 8M (1M ×8/512K ×6) Bit Falsh Memory(單5V 電源電壓1M ×8/512K ×6位閃速存儲(chǔ)器)
中文描述： 8米（1米× 8/512K × 6）位Falsh內(nèi)存（單5V的電源電壓100萬(wàn)× 8/512K × 6位閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 20/51頁(yè)
文件大?。?/td> 642K
代理商： MBM29F800B-90
20
MBM29F800T
-90/-12
/MBM29F800B
-90/-12
The DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devicev locks out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing limits, the
DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly
used.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the
second status check, the command may not have been accepted.
Refer to Table 7: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
Notes:
1. These status flags apply when outputs are read from a sector that has been erase-suspended.
2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode (DQ
2
toggles while
DQ
6
does not). See also Table 7 and Figure 17.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from the erasing sector.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
toggles
Erase Suspend Program
DQ
7
(Note 2)
toggles
1 (Note 2)
相關(guān)PDF資料
PDF描述
MBM29F800B 8 M (1 M×8/512 K×16) BIT Flash Memory(8 M (1 M×8/512 K×16) 位單5V 電源電壓閃速存儲(chǔ)器)
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