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參數(shù)資料
| 型號： | MBM29LV002B |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2M (256K ×8) Flash Memory(CMOS 2M(256K ×8)位 單5V 電源電壓閃速存儲器) |
| 中文描述： | 200萬的CMOS（256K × 8）快閃記憶體（200萬的CMOS（256K × 8）位單5V的電源電壓閃速存儲器） |
| 文件頁數(shù)： | 16/45頁 |
| 文件大?。?/td> | 279K |
| 代理商： | MBM29LV002B |
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16
MBM29LV002T/MBM29LV002B
DQ
6
Toggle Bit I
The MBM29LV002T/002B also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 2
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 50
and then drop back into read mode, having changed none of the data.
μ
s and then stop
μ
s
Either CE or OE toggling will cause the DQ
cause DQ
6
to toggle.
6
to toggle. In addition, an Erase Suspend/Resume command will
See Figure 11 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully
completed. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Table 2.
5
will indicate if the program or erase time has exceeded the specified limits. Under these conditions DQ
5
will
If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may
not be reused. However, other sectors are still functional and may be used for the program or erase operation.
The device must be reset to use other sectors. Write the Reset command sequence to the device, and then
execute program or erase command sequence. This allows the system to continue to use the other active sectors
in the device.
If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination
of sectors are bad.
If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing
that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused).
The DQ
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing limits, the
DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly
used.
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
DQ
3
Sector Erase Timer
After the completion of the initial Sector Erase command sequence the sector erase time-out will begin. DQ
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial Sector Erase
command sequence.
3
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
3
may
3
is high (“1”) the internally controlled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29LV002T | CMOS 2M (256K ×8) Flash Memory(CMOS 2M(256K ×8)位 單5V 電源電壓閃速存儲器) |
| MBM29LV003T-12 | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| MBM29LV002B-10 | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| MBM29LV002B-12 | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| MBM29LV002T-10 | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV002BC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12PNS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12PTN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
| MBM29LV002BC-12PTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:2M (256K x 8) BIT |
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