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參數(shù)資料
| 型號： | MBM29PDS322TE10PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | Replaced by TPS2046B : 0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC -40 to 85 |
| 中文描述： | 2M X 16 FLASH 1.8V PROM, 100 ns, PBGA63 |
| 封裝： | PLASTIC, FBGA-63 |
| 文件頁數(shù)： | 20/66頁 |
| 文件大?。?/td> | 694K |
| 代理商： | MBM29PDS322TE10PBT |
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MBM29PDS322TE/BE
10/11
20
Standby Mode
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the
other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
± 0.3 V.
Under this condition, the current consumed is less than 5
μ
A Max. During Embedded Algorithm operation, V
CC
active current (I
CC2
) is required even CE = “H”. The device can be read with standard access time (t
CE
) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
± 0.3 V (CE
= “H” or “L”). Under this condition the current consumed is less than 5
μ
A Max. Once the RESET pin is taken
high, the device requires t
RH
as wake up time for outputs to be valid for read access.
In the standby mode, the outputs are in the high impedance state, independently of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of the device
data. This mode can be useful in the application such as a handy terminal which requires low power consumption.
To activate this mode, the device automatically switches themselves to low power mode when the device ad-
dresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode.
Under the mode, the current consumed is typically 50
μ
A (CMOS Level).
During simultaneous operation, V
CC
active current (I
CC2
) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically, and the device reads the data for changed addresses.
Output Disable
With the OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(10.0 V to 11.0 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the device outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are DON’T CARES except A
6
, A
3
, A
2
, A
1
, and A
0
. (See Table 3.)
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A
9
pin. The command sequence is
illustrated in Table 4. (Refer to Autoselect Command section.)
In the command Autoselect mode, the bank addresses BA; (A
20
to A
12
) must point to a specific bank during the
third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while
array data can be read from the other bank.
A read cycle from address (BA)00h returns the manufacturer’s code (Fujitsu = 04h). And a read cycle from
address (BA)01h, (BA)0Eh to (BA)0Fh returns the device code. (See Tables 5.1 to 5.4.)
In case of applying V
ID
on A
9
, since both Bank 1 and Bank 2 enter Autoselect mode, the simultaneous operation
can not be executed.
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