參數(shù)資料
型號(hào)： MC13xx
廠商： Motorola, Inc.
英文描述： CONVERTER, DC/DC, 1O/P, 5W, 3.3V; Power rating:5W; DC/DC Converter O/P type:Single; Voltage, input max:36V; Voltage, input min:9V; Voltage, output:3.3V; Depth, external:10.2mm; Length / Height, external:31.8mm; Width, RoHS Compliant: Yes
中文描述： 通用窄帶調(diào)頻接收器集成電路
文件頁(yè)數(shù)： 41/68頁(yè)
文件大?。?/td> 1316K
代理商： MC13XX
MC13110A/B MC13111A/B
41
MOTOROLA ANALOG IC DEVICE DATA
By substituting into equation (4), solve for T2:
T2
tan
Qp
2
4
wp
(8)
By choosing a value for wp and Qp, T1 and T2 can be
calculated. The choice of Qp determines the stability of the
loop. In general, choosing a phase margin of 45 degrees is a
good choice to start calculations. Choosing lower phase
margins will provide somewhat faster lock–times, but also
generate higher overshoots on the control line to the VCO.
This will present a less stable system. Larger values of phase
margin provide a more stable system, but also increase
lock–times. The practical range for phase margin is 30
degrees up to 70 degrees.
The selection of wp is strongly related to the desired
lock–time. Since it is quite complicated to accurately
calculate lock time, a good first order approach is:
T_lock
3
wp
(9)
Equation (9) only provides an order of magnitude for lock
time. It does not clearly define what the exact frequency
difference is from the desired frequency and it does not show
the effect of phase margin. It assumes, however, that the
phase detector steps up to the desired control voltage
without hesitation. In practice, such step response approach
is not really valid. The two input frequencies are not locked.
Their phase maybe momentarily zero and force the phase
detector into a high impedance mode. Hence, the lock times
may be found to be somewhat higher.
In general, wp should be chosen far below the reference
frequency in order for the filter to provide sufficient
attenuation at that frequency. In some applications, the
reference frequency might represent the spacing between
channels. Any feedthrough to the VCO that shows up as a
spur might affect adjacent channel rejection. In theory, with
the loop in lock, there is no signal coming from the phase
detector. But in practice leakage currents will be supplied to
both the VCO and the phase detector. The external
capacitors may show some leakage, too. Hence, the lower
wp, the better the reference frequency is filtered, but the
longer it takes for the loop to lock.
As shown in Figure 98, the open loop gain at wp is 1 (or
0 dB), and thus the absolute value of the complex open loop
gain as shown in equation (3) solves C1:
C1
KpdKoT1
w2KnT2
1
wpT2
2
1
wpT1
2
(10)
With C1 known, and equation (2) solve C2 and R2
:
C2
C1T2
T1
T2
C2
1
(11)
R2
(12)
The VCO gain is dependent on the selection of the
external inductor and the frequency required. The free
running frequency of the VCO is determined by:
f
1
2
LCT
(13)
In which L represents the external inductor value and CT
represents the total capacitance (including internal
capacitance) in parallel with the inductor. The VCO gain can
be easily calculated via the internal varicap transfer curve
shown below.
Figure 99. Varicap Capacitance
versus Control Voltage
0
15
,
V
14
12
13
11
10
9.0
8.0
7.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
As can be derived from Figure 99, the varicap capacitance
changes 1.3 pF over the voltage range from 1.0 V to 2.0 V:
Cvar
1.3 pF
V
(14)
Combining (13) with (14) the VCO gain can be determined
by:
K
o
1
jw
1
2
L CT
Cvar
2
1
2
L C
T
Cvar
2
(15)
Although the basic loopfilter previously described provides
adequate performance for most applications, an extra pole
may be added for additional reference frequency filtering.
Given that the channel spacing in a CT–0 telephone set is
based on the reference frequency, and any feedthrough to
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