參數(shù)資料
型號(hào)： MC13xx
廠商： Motorola, Inc.
英文描述： CONVERTER, DC/DC, 1O/P, 5W, 3.3V; Power rating:5W; DC/DC Converter O/P type:Single; Voltage, input max:36V; Voltage, input min:9V; Voltage, output:3.3V; Depth, external:10.2mm; Length / Height, external:31.8mm; Width, RoHS Compliant: Yes
中文描述： 通用窄帶調(diào)頻接收器集成電路
文件頁(yè)數(shù)： 44/68頁(yè)
文件大?。?/td> 1316K
代理商： MC13XX
MC13110A/B MC13111A/B
SERIAL PROGRAMMABLE INTERFACE
44
MOTOROLA ANALOG IC DEVICE DATA
Microprocessor Serial Interface
The Data, Clock, and Enable (“Data”, “Clk”, and “EN”
respectively) pins provide a MPU serial interface for
programming the reference counters, the transmit and
receive channel divide counters, the switched capacitor filter
clock counter, and various other control functions. The “Data”
and “Clk” pins are used to load data into the MC13111A/B
shift register (Figure 109). Figure 105 shows the timing
required on the “Data” and “Clk” pins. Data is clocked into the
shift register on positive clock transitions.
Figure 105. Data and Clock Timing Requirement
Data,
Clk, EN
Data
Clk
tsuDC
tr
tf
50%
50%
th
10%
90%
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–bit address is loaded
into the shift register and latched into the 8–bit address latch
register. Then, up to 16–bits of data is loaded into the shift
register and latched into the data latch register. It is specified
by the address that was previously loaded. Figure 106 shows
the timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 106. Enable Timing Requirement
Clk
tsuEC
EN
50%
50%
50%
trec
Previous Data Latched
Last
Clock
First
Clock
50%
The state of the “EN” pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 107 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first. A minimum of four “Clk” rising edge
transition must occur before a negative “EN” transition will
latch data or an address into a register.
Figure 107. Microprocessor Interface
Programming Mode Diagrams
Data
Latch
8–Bit Address
EN
Data
EN
Address Register Programming Mode
16–Bit Data
Data Register Programming Mode
Latch
Latch
MSB
MSB
LSB
LSB
The MPU serial interface is fully operational within 100
μ
s
after the power supply has reached its minimum level during
power–up (see Figure 108). The MPU Interface shift
registers and data latches are operational in all four power
saving modes; Inactive, Standby, Rx, and Active Modes.
Data can be loaded into the shift registers and latched into
the latch registers in any of the operating modes.
Figure 108. Microprocessor Serial
Interface Power–Up Delay
VCC
tpuMPU
2.7 V
Data,
Clk, EN
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