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| 型號： | MC13xx |
| 廠商： | Motorola, Inc. |
| 英文描述： | CONVERTER, DC/DC, 1O/P, 5W, 3.3V; Power rating:5W; DC/DC Converter O/P type:Single; Voltage, input max:36V; Voltage, input min:9V; Voltage, output:3.3V; Depth, external:10.2mm; Length / Height, external:31.8mm; Width, RoHS Compliant: Yes |
| 中文描述： | 通用窄帶調頻接收器集成電路 |
| 文件頁數(shù)： | 56/68頁 |
| 文件大?。?/td> | 1316K |
| 代理商： | MC13XX |
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MC13110A/B MC13111A/B
56
MOTOROLA ANALOG IC DEVICE DATA
Voltage Reference Adjustment
An internal 1.5 V bandgap voltage reference provides the
voltage reference for the “BD1 Out” and “BD2 Out” low battery
detect circuits, the “PLL Vref” voltage regulator, the “VB”
reference, and all internal analog ground references. The
initial tolerance of the bandgap voltage reference is
±
6%. The
tolerance of the internal reference voltage can be improved to
±
1.5% through MPU serial interface programming. During
final test of the telephone, the battery detect threshold is
measured. Then, the internal reference voltage value is
adjusted electronically through the MPU serial interface to
achieve the desired accuracy level. The voltage reference
register value should be stored in ROM during final test so
that it can be reloaded each time the MC13110A/B or
MC13111A/B is powered up (see Figure 131).
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Bit #3
Bit #2
Bit #1
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0
0
0
1
1
1
Bit #0
#
Amount
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
10
12
4
5
6
–5.4%
–4.2%
–3.0%
–1.8%
+1.8 %
+3.0 %
+4.2 %
+5.4 %
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11
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter clock
divider is show in Figure 132. There is a fixed divide by 2 after
the programmable divider. The switched capacitor filter clock
value is given by the following equation;
(SCF Clock) = F(2nd LO) / (SCF Divider Value * 2).
The scrambler modulation clock frequency (SMCF) is
proportional to the SCF clock. The following equation defines
its value:
SMCF = (SCF Clock)/40
The SCF divider should be set to a value which brings the
SCF Clock as close to 165.16 kHz as possible. This is based
on the 2nd LO frequency which is chosen in Figure 114.
Figure 132. SCF Clock Divider Circuit
LO2 Out
6–b
Programmable
SCF Clock Counter
LO2 In
2nd LO
Crystal
SCF
Clock
Divide
By 2.0
Scrambler
Modulation
Clock
Divide
By 40
MC13110A/B
only
Corner Frequency Programming for MC13110A/B and
MC13111A/B
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 133
and 134. It is important to note, that all filter corner
frequencies will change proportionately with the SCF Clock
Frequency and Scrambler Modulation Frequency. The
power–up default SCF Clock divider value is 31.
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160 00
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SCF Clock
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62
Divide
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3.879
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Corner
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3.700
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Corner
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4.129
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Frequency
Lower Corner
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250.0
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Upper Corner
31
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165.16
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3.650
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19. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
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