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參數(shù)資料
| 型號： | MC33397 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control(帶SPI和并口輸入控制的2或6低端開關(guān)) |
| 中文描述： | 雙/六角低側(cè)開關(guān)SPI和并行輸入控制（帶的SPI和并口輸入控制的2或6低端開關(guān)） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 562K |
| 代理商： | MC33397 |
33397
14
Go to: www.freescale.com
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33397 is a versatile dual-mode low-side switch that can
be output-configured as two 333 m
open drain outputs in the
dual mode or as six 900 m
open drain outputs in the hex mode
(R
DS(ON)
@ 25°C).
Each open drain output has internal current limit and short-
circuit protection. Current limit is typically 1.5 A, with 2.0 A
maximum. The outputs can be input controlled via parallel
inputs or the SPI. Three inputs provide parallel control, while a
serial 8-bit word provides SPI control of the outputs. Output fault
detection capability includes OFF-state open loads and ON-
state short-to-battery conditions. Individual output faults are
latched into the fault register and serially shifted out during
serial communication to the 33397. The 33397 has both
overvoltage and undervoltage shutdown.
A low quiescent current sleep slate feature can be enabled
or disabled on command via the SPI port.
FUNCTIONAL PIN DESCRIPTION
V
DD
Logic power supply pin.
A0–A5
A0–A5 are the drains of the 1.2
(max.) MOSFETs. They
each have an internal voltage clamp of 50 V (min.) to clamp
inductive loads during turn-off. When enabled, they are each
internally current limited to a maximum of 2.0 A. If any output is
in current limit (output voltage >3.0 V) for a time greater than
t
SS
, the output will be disabled for a time t
REF
and then try to
turn on again. When disabled, open circuits are detected if the
output is less than 3.0 V for a time of t
SS
. Either type of fault is
reported as a fault on the SPI output word. If
EN
input is high
and SPI bit 7=1, the pull-down current sources on the outputs
are disabled to minimize V
DD
supply current.
In hex mode, all six outputs are independent. Outputs A0,
A1, and A2 are controlled by either the SPI input word bits 0, 1,
and 2, respectively, or parallel inputs P0, P1, and P2. Outputs
A3, A4, and A5 are controlled only by SPI input word bits 3, 4,
and 5, respectively.
In dual mode, outputs A0, A4, and A5 are all controlled
simultaneously by input P0 or by SPI bits 0, 4, and 5. All three
bits must be high to enable this output via the SPI. Outputs A1,
A2, and A3 are all controlled simultaneously by input P1 or by
SPI bits 1, 2, and 3. All three bits must be high to enable this
output via the SPI.
P0–P2
In hex mode, P0 is the parallel input to control output A0. It is
OR'd with SPI bit 0 to enable output A0. Either one will enable
output A0. In dual mode, P0 controls outputs A0, A4, and A5
simultaneously. P0 has a pull down current of 10 μA. It is
ignored when
EN
is high and bit 7=1.
In hex mode, P1 is the parallel input to control output A1. It is
OR'd with SPI bit 1 to enable output A1. Either one will enable
output A1. In dual mode, P1 controls outputs A1, A2, and A3
simultaneously. P1 has a pull-down current of 10 μA. It is
ignored when
EN
is high and bit 7=1.
In hex mode, P2 is the parallel input to control output A2. It is
OR'd with SPI bit 2 to enable output A2. Either one will enable
output A2.
P2 also is used to program the 33397 to either a dual or hex
output device. The 33397 will be the hex mode if P2 is biased
above 0.75*V
DD
(typical) or below 0.25*V
DD
(typical). Normal
5.0 V control logic on this parallel input will maintain the 33397
in hex mode and allow control of output A2. If 0.25*V
DD
<P2<0.75*V
DD
for more than 10 μs, the 33397 will switch to
dual mode. P2 has a pull-down current of 10 μA. It is ignored
when EN is high and bit 7=1.
V
PWR
V
PWR
is used to sense an overvoltage condition on the
supply pin. When the voltage on V
PWR
exceeds V
OV
, all outputs
are disabled for the duration of the overvoltage condition. If
V
PWR
is grounded, overvoltage shutdown is disabled. V
PWR
threshold can be modified with an external resistor divider if
higher thresholds are desired.
SCLK
SCLK is the clock for the serial interface.
SI
SI is the serial input for the SPI port. When
CS
is low, SI is
read on the positive edge of SCLK and SO is updated on the
falling edge. When
CS
is high, SI is ignored. SI has a pull-down
current source to pull it low in the event of an open circuit.
SO
SO is the serial output of the SPI port. When
CS
goes low,
SO outputs bit 7 of the output word. On each falling edge of
SCLK, SO will shift the next SPI output bit until on the eighth
SCLK falling edge the bit present on SI during the first rising
edge will appear. In this way devices can be daisy-chained to
operate on a common
CS
. When
CS
is high, SO is high
impedance.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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