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參數(shù)資料
| 型號： | MC33397 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control(帶SPI和并口輸入控制的2或6低端開關(guān)) |
| 中文描述： | 雙/六角低側(cè)開關(guān)SPI和并行輸入控制（帶的SPI和并口輸入控制的2或6低端開關(guān)） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 562K |
| 代理商： | MC33397 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33397
15
CS
CS
is the chip select to enable the SPI interface. When
CS
is
high, no SPI communication is possible. When
CS
goes low, SI
will be read on each rising SCLK edge and SO will shift on each
SCLK falling edge. When
CS
goes high, the bits present in the
SPI input register will be interpreted as the SPI input command.
Also when
CS
goes high, all faults that were latched into the SPI
output register are cleared. If faults are still present on outputs,
they will be re-latched after t
SS
.
EN
EN
must be low for complete IC functionality in either the dual
or hex mode. When
EN
transitions low while in the sleep mode
or when the IC is powered up from V
DD
, a power-up timer of
40 μs is started to allow the 33397 to determine which mode it
is in (hex or dual). During this time all parallel inputs and serial
control SPI bits will be ignored and all outputs will remain off. If
EN
transitions low when not in the sleep mode, this “dead” time
will not occur.
If a one was written to bit 7, the 33397 will be in the sleep
mode when
EN
goes high. In this mode all SPI registers are
reset to zero and all faults are cleared. No fault detection is
possible. The standby supply current on V
DD
and V
PWR
is
minimized.
APPLICATIONS
A voltage on the P2 input pin determines the mode. All six
outputs can operate either independently (hex mode)
(Figure 15) or in paralleled groups of three (dual mode)
(Figure 16). In the dual mode, outputs A0, A1, and A2 are
controlled by parallel inputs P0, P1, and P2, respectively, and
they are also controlled by the SPI port with which they are
OR’d. On the other hand, outputs A3, A4, and A5 are controlled
only
through the SPI port. When the voltage on P2 is between
0.25 V
DD
and 0.75 V
DD
(i.e., when P2 is held at an intermediate
voltage, neither high nor low), the 33397 operates in the dual
mode. However, the P2 pin must stay at that level for a
minimum specified time. In this mode, outputs A0, A4, and A5
are all controlled in parallel by input P0. Outputs A1, A2, and A3
are all controlled in parallel by input P1. Both outputs can also
be controlled via the SPI port as well, but only if the three
outputs are commanded ON at the same time.
Figure 15. Hex Mode Application Circuit
Figure 16. Dual Mode Application Circuit
33397
A5
A4
SCLK
SI
GND
GND
GND
GND
SO
CS
A3
A2
V
PWR
A0
P2
P1
GND
GND
GND
GND
P0
EN
A1
V
DD
V
BAT
V
BAT
V
DD
V
DD
(Optional)
Parallel Inputs
From Microprocessor
To Micro-
processor
V
BAT
A5
A4
SCLK
SI
GND
GND
GND
GND
SO
CS
A3
A2
V
PWR
A0
P2
P1
GND
GND
GND
GND
P0
EN
A1
V
DD
(Optional)
Parallel Inputs
V
BAT
33397
V
DD
From Microprocessor
To Micro-
processor
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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